Cadence - MIMcaps become unrecognised after introduction of a new component

[BartasA]

Hi,

I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBL. Component A has a large MIMcap (multiplier 60) with a 1.8V, 5 V, floating 5V and HV inputs, B is a logic block at 1.8V, and component C has two separate 1.8 V supplies (AVDD and DVDD) and is covered by MIMcap as well. Now I am making a higher level component D that includes A, B and C together.

My issue is that although components A, B and C are all DRC/LVS clean, after I instantiated A, B, C in component D, all of the MIMcaps of A become not recognised in the schematic. I could not initially find the issue so I did the following in the schematic and layout:

1. Instantiated only A with all ports NC. Result: LVS clean
2. Added supply pins to A. Result: LVS clean.
3. Added all other pins apart from the ones that should come from B and C. Result: LVS clean.
3. Include component B and connect to A. Result: MIMcap not recognised. >> I then pinpointed this to having VSS of A (5V NBL) connected to VSS of B (1V8 NBL). Really not sure why this is an issue...
3.b Create a separate ground pin for A and B. Result: LVS clean.

At this point I have LVS clean and continue with the incremental approach:
4. Instantiate C with all pins except substrate NC. Place it anywhere in the layout away from A and B + connect SUB through M1. Result: LVS not clean, MIMcaps not recognised in the schematic and all nodes related to these capacitors not recognised correctly either.

Does anyone know what could cause such an error when all components are LVS clean? Where could I find a clue about this?
Does anyone have any ideas why having VSS connected (point 3) and adding a new component (point 4) results in the same error?

One thing to note here is that the MIMcap in A is a bootstrapped capacitor that generates a floating 5 V supply, but I do not see the direct link of it being the issue...

Any help is highly appreciated!

 

[dick_freebird]

Look to your supply nets and the plates used in each. Caps may be
getting pruned as shorted, or shorting may fail the extraction logic.

Like say A and C used M6 vdd and M5 vss, but B used M6 vss and
M5 vdd (or one of your various).

Probe the nets that are supposed to be attached to the "missing"
caps and see what highlights. Too little? Too much? Both plates,
indicating a short? And maybe because MIM is just metal terminal
short rules are not applied. Or maybe they were reported and you
didn't notice.

 

[dick_freebird]

Also look to cell butting, and any possibility that the plates of
two separate cells, may "merge" when co-placed and then two
separate MIMs become one flat-extracted oversized cap while
the "other one" is subsumed in the first?

If your cell which still has MIMs, is delivering size error as if it's
extra fat, this could be it.