MIG phy_init_done signal does not goes high

[syedshan]

Hi every one...

I am dealing with memory controller for DDR3 for virtex-6 generated by xilinx MIG.
I tried the simulation the .bat process etc. and it ran fine then I shifted to take the individual finels and call them to make a project using project navigator.

I tried the the functional simulation first... and to my horror after two days or more, I am unable to get the signals show some proper response... Leaving other signals, only if I talk about the phy_init_done signal (which is generated by the PHY layer, to indicate that physical layer is ready for the communication now, i.e. initial calibration done) does not goes high to start the operation for write/read.

I cannot understand what is the issue. Since I connected the DDR3 memory model that is generated during the MIG design, the communication should be proper.
Does any one had similar experience.
By the way I have this warning message generated by ISIM while starting simulation

WARNING: File "D:/Coding/Xilinx/DDR3_write_read_test/ipcore_dir/secondDDR3/user_design_xil/test_verilog.v" Line 31. For instance test_verilog/Inst_ddr3/, width 13 of formal port addr is not equal to width 15 of actual signal ddr3_addr.

I am sure this might have something to deal with this, but how come this message appear when the things I done is just copy the files and put in the project navigator to develop new project. How to deal with this, since it is a simulation memory model and changing the address bits manually is nor a proper method I guess.

 

[mcsattle]

Hi every one...

I am dealing with memory controller for DDR3 for virtex-6 generated by xilinx MIG.
I tried the simulation the .bat process etc. and it ran fine then I shifted to take the individual finels and call them to make a project using project navigator.

I tried the the functional simulation first... and to my horror after two days or more, I am unable to get the signals show some proper response... Leaving other signals, only if I talk about the phy_init_done signal (which is generated by the PHY layer, to indicate that physical layer is ready for the communication now, i.e. initial calibration done) does not goes high to start the operation for write/read.

I cannot understand what is the issue. Since I connected the DDR3 memory model that is generated during the MIG design, the communication should be proper.
Does any one had similar experience.
By the way I have this warning message generated by ISIM while starting simulation



I am sure this might have something to deal with this, but how come this message appear when the things I done is just copy the files and put in the project navigator to develop new project. How to deal with this, since it is a simulation memory model and changing the address bits manually is nor a proper method I guess.

I can't give much insight other than the Warning you're seeing is most likely not the cause. You probably have 15 pins setup, but the ddr module itself only uses 13 address bits instead of 15. If you want to get rid of this error, set up some sort of intermediate signal to set the last 2 bits to '0'.

-Matt