vakost
Newbie level 2
Hello. I am using Xilinx EDK 12.1.
I have a question regarding microblaze but first, let me explain how I understand things to be, so you can correct me if I am wrong.
1. First I create my design with XPS. After I finish with all the hardware configuration and writing in VHDL, I create the hardware with the ISE.
2. Then, I write C code in SDK and compile.
3. In the "Program FPGA" window, there are 3 file inputs. First, the bitstream, then the BMM file and then the ELF file to initialize in the Block RAM.
So, what is happening? The bitstream is the binary file of the whole microblaze, the BMM is the Block Ram Memory Map and the ELF file is the instruction code yes?
Can you verify that this is correct?
Now, what I want is to create one big file that will contain all the information from these files together.
Is it doable? I want that because I want to download the whole thing in a labview project (using the CLIP node) and I cannot do it through JTAG (it is a PXI design with a Virtex V and only labview can have access there through the PXI bus).
Thank you very much for any info.
Bill.
I have a question regarding microblaze but first, let me explain how I understand things to be, so you can correct me if I am wrong.
1. First I create my design with XPS. After I finish with all the hardware configuration and writing in VHDL, I create the hardware with the ISE.
2. Then, I write C code in SDK and compile.
3. In the "Program FPGA" window, there are 3 file inputs. First, the bitstream, then the BMM file and then the ELF file to initialize in the Block RAM.
So, what is happening? The bitstream is the binary file of the whole microblaze, the BMM is the Block Ram Memory Map and the ELF file is the instruction code yes?
Can you verify that this is correct?
Now, what I want is to create one big file that will contain all the information from these files together.
Is it doable? I want that because I want to download the whole thing in a labview project (using the CLIP node) and I cannot do it through JTAG (it is a PXI design with a Virtex V and only labview can have access there through the PXI bus).
Thank you very much for any info.
Bill.