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You can provide your program file to your fpga vendor, and he will do the rest things. And the ASIC from the fpga has the same performace as FPGA you designed.
If you want a true asic , you have to choose a foundry and have other valuable tools and lots of time to do it.
You should minimize changes between FPGA and ASIC. Partition the design such that modifications are made only to necessary modules, eg. specific cores, RAM modules and clocking logic. Like what 'cbh1024' said, write your code as portable as possible. It will greatly minimize the verification effort.
Leon may be an good example of portable code for ASIC and FPGA uses. Of course, you have to design some technology primitive in a separate file that allow technology porting and maintenance easier.
Leon supports a lot of vendor tools and fpga/asic technologies through some technology/vendor dependent files, even though, the leon core is still very clean, and independent of (at least) technology uses.
My personal study on the FPGA to ASIC migration will be based on
which technologies will be used.
Basically the gatearray product line offered by most of the foundry
will be 0.25um or above. Only the standard cell can have the state-of-the-art processing service.
As a result, timing will be a major concern. Of course the blockRAM in XILINX is hard to be included in the gatearray service though there
are lots of design house can do the netlist and RTL sign-off for you.
I do believe that there is still a great room to use the low-cost FPGA
such as those in ACTEL/Altera/XILINX. So before jumping to ASI,
production volumn will be the major factor.