Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Methodology: from fpga to asic?

Status
Not open for further replies.

whatever

Junior Member level 1
Junior Member level 1
Joined
May 2, 2002
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
73
How to convert the fpga to asic quickly, smoothly, and efficiently?

Thx in advance.
 

jetmarc

Member level 3
Member level 3
Joined
Dec 17, 2001
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,235
whatever said:
How to convert the fpga to asic quickly, smoothly, and efficiently?
Thx in advance.

ACTEL offers an upgrade path for its FPGA series. They may not be as cost-effective as a "normal" ASIC, but the migration is easy and fast.

jetmarc
 

wjhzhx

Junior Member level 1
Junior Member level 1
Joined
Mar 25, 2002
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
92
Altera and Xilinx have the same upgrade path as jetmarc said
 

linuxluo

Full Member level 6
Full Member level 6
Joined
Jul 26, 2002
Messages
331
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
2,514
Hi,
You can provide your program file to your fpga vendor, and he will do the rest things. And the ASIC from the fpga has the same performace as FPGA you designed.
If you want a true asic , you have to choose a foundry and have other valuable tools and lots of time to do it.
 

cbh1024

Newbie level 4
Newbie level 4
Joined
May 31, 2001
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
29
Converting from FPGA to ASIC

Try to write clean synthesizable synchronous design VHDL/Verilog codes that can be ported across multiple platforms and multiple implementations.

Take the same piece of Verilog or VHDL code and retarget to ASIC
cells with minimum or no code change.
 

aramis

Member level 3
Member level 3
Joined
Apr 7, 2002
Messages
64
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
418
yes,
i agree with cbh1024
if your code is written "portable"
it can be synthesis either in FPGA or ASIC
(except the vendor component instance)
 

ntxp

Member level 2
Member level 2
Joined
May 29, 2002
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
342
Did anyone tried the fpga vendor path to make ASIC?
Could share with us the price/lead time involved?
 

corgan

Member level 3
Member level 3
Joined
Jan 15, 2002
Messages
55
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
319
Except write the fully synthesizable code,
beware of the SRAM part if you use internal SRAM for buffer/FIFO. You have to
take care of the timing to get correct result.
 

prozess

Junior Member level 3
Junior Member level 3
Joined
Sep 28, 2001
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
94
But I think the coding style of FPGA and ASIC are something diferent. So it may be for some reasons to write some code but they are not suitable for the other one.
 

jkfoo

Member level 1
Member level 1
Joined
May 17, 2001
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
261
You should minimize changes between FPGA and ASIC. Partition the design such that modifications are made only to necessary modules, eg. specific cores, RAM modules and clocking logic. Like what 'cbh1024' said, write your code as portable as possible. It will greatly minimize the verification effort.
 

ntxp

Member level 2
Member level 2
Joined
May 29, 2002
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
342
Leon may be an good example of portable code for ASIC and FPGA uses. Of course, you have to design some technology primitive in a separate file that allow technology porting and maintenance easier.

Leon supports a lot of vendor tools and fpga/asic technologies through some technology/vendor dependent files, even though, the leon core is still very clean, and independent of (at least) technology uses.

ntxp
 

calvinhorng

Member level 4
Member level 4
Joined
Jul 18, 2002
Messages
73
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
539
GATEarray or standard cell

My personal study on the FPGA to ASIC migration will be based on
which technologies will be used.
Basically the gatearray product line offered by most of the foundry
will be 0.25um or above. Only the standard cell can have the state-of-the-art processing service.

As a result, timing will be a major concern. Of course the blockRAM in XILINX is hard to be included in the gatearray service though there
are lots of design house can do the netlist and RTL sign-off for you.

I do believe that there is still a great room to use the low-cost FPGA
such as those in ACTEL/Altera/XILINX. So before jumping to ASI,
production volumn will be the major factor.

That is my personal opinion.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top