Method to provide constraints in DC

[manik_vivek_82]

Hi,
I recently started working on DC. How do you actually go abt deciding the values of the constraints. I have gone thru the SOLD manual, but still confused. Can anyone suggest something?

 

[nittinsharma80]

Hi Vivek,
i am also a newbie for dc but i can suggets my understanding about the values
the values of the constraints depend on the design's timing and area constraints and the library that you will be using for synthesis. for e.g. the creat_clock's -period constraints will decide synthesis of the desing for the corresponding clock freq. also the set min/max values of the capacitence etc will be determined by the standard cell library that you are using for synthesis and furthersteps
group kindly correct me if i am wrong/incomplete etc.
the discussion on dc can help so many people
regards

 

[manik_vivek_82]

I agree.
Given, a design or a project, how do i start with the process of determining the constraints during the synthesis process? Moreover, how do i find the constraints such as input delay, output delay?
If we get a negative slack, and find the path that violates the timing, how do i go abt the process of reducing the slack? Give some conclusive steps..

 

[spauls]

Constraints are of various types

speed -> Timing Constraintas ( I/P delay O/P delay both max and min)
Optimization -> Area ( Max Area)
Design rule constraints - Max fanout , max load, max capacitance.

 

[haosg]

the i/o input/output delay should be decided by the chip's environment