Well, that depends on the kind of type of D-flip-flop. I assume you need one that both have a set and reset input in order to being able to try get it into metastability.
This theory is out of my comfort zone, but I will guess that it it stabilize pretty fast without too many cycles.
Because the complexity of the impedance of set/reset input pin and possible connected wiring, I cannot see why there should be a "formula" for this. Also internal difference in delay in internal logic would make it hard to predict how many cycles it takes to settle. And even yet you will have internal crossover that also may affect the number of cycles before settling.
Just for the sake of having an answer: Wery quicly (time from when you release Set and Reset).