Metastability in FPGAs

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Tapojyoti Mandal

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I have been studying about metastability and its details. It is said that synchronization chain registers are used to solve the problem of metastability. I want to know what is the importance of parameter 'Tmet' in calculation of MTBF and what is meant by 'timing slack' of registers in synchronization chain?
 

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The document states that Tmet is the sum of timing slacks between registers.

The timing slack is the difference between the clock period and the sum of the Tco+Tpd+Tsu of the timing path (i.e. the setup time between the registers. It's how much timing margin you have.
 

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