Metastability in FPGAs

[Tapojyoti Mandal]

I have been studying about metastability and its details. It is said that synchronization chain registers are used to solve the problem of metastability. I want to know what is the importance of parameter 'Tmet' in calculation of MTBF and what is meant by 'timing slack' of registers in synchronization chain?

 

[ads-ee]

The document states that Tmet is the sum of timing slacks between registers.

The timing slack is the difference between the clock period and the sum of the Tco+Tpd+Tsu of the timing path (i.e. the setup time between the registers. It's how much timing margin you have.