Memory synchronisation question

[rg_ming]

Hi,

I'm using Xilinx FPGA and trying to write a memory controller with verilog to save data to a pseudo-SRAM chip. The memory is working on a sync burst mode. What I need to do is to save the data come out of the ADC to the memory. The ADC works on 100MSPS, the frequency of the memory I have is 80MHz. How can I synchronise the ADC and memory to ensure correct data saving.

Thanks in advance.

 

[vipinlal]

How many bit ADC is that you are using? And by sync burst mode did you mean that you are writing 8/16 bits(or some thing like that) to the memory at a time.

I think the data can be written correctly by adjusting the clocks at which the data is written into the memory.And this clock freq will depend upon the ADC sample width and memory burst size.

--vipin
https://vhdlguru.blogspot.com/

 

[rg_ming]

How many bit ADC is that you are using? And by sync burst mode did you mean that you are writing 8/16 bits(or some thing like that) to the memory at a time.

I think the data can be written correctly by adjusting the clocks at which the data is written into the memory.And this clock freq will depend upon the ADC sample width and memory burst size.

--vipin
https://vhdlguru.blogspot.com/

Thanks vipin

It's a 10-bit ADC, and the data bus of the memory is 16 bits, I'm planning to do some rearrangements of the data first. And the burst length is continuous burst, it's 128 words.

There is a question that I'm still not very clear, does the clock input to the memory have anything to do with the frequency of the memory? Or is there any reqirement to the input clock of the memory?

 

[vipinlal]

By 128 words do you mean 128*16 bits?

Your ADC works at 100 msps.So on an average excluding the overhead bits you have 10 Mega samples per second coming into your system.

And since the data is written continuously you can have a RAM based shift register(available with core generator) for carrying the 128 words. ADC data is written into the above said RAM based shift register and data is read from this register to the SRAM.The write clk here is 10 MHz(corresponding to 10 Mega samples per sec) and read clock is also 10 MHz or more (assuming you want to read from shift register without losing any data) .

Here I am assuming that you dont want to use the MSB 6 bits(16-10) of the memory for easier coding.

Input clock, I meant read and write clocks.They have a max value defined for each memory design.Here it wont be a problem.

 

[rg_ming]

By 128 words do you mean 128*16 bits?

Your ADC works at 100 msps.So on an average excluding the overhead bits you have 10 Mega samples per second coming into your system.

And since the data is written continuously you can have a RAM based shift register(available with core generator) for carrying the 128 words. ADC data is written into the above said RAM based shift register and data is read from this register to the SRAM.The write clk here is 10 MHz(corresponding to 10 Mega samples per sec) and read clock is also 10 MHz or more (assuming you want to read from shift register without losing any data) .

Here I am assuming that you dont want to use the MSB 6 bits(16-10) of the memory for easier coding.

Input clock, I meant read and write clocks.They have a max value defined for each memory design.Here it wont be a problem.

Yes, 1 word in the memory I have equals 16 bits. The memory will write up to 128 sequential locations with a single address.

Thanks vipin.