By 128 words do you mean 128*16 bits?
Your ADC works at 100 msps.So on an average excluding the overhead bits you have 10 Mega samples per second coming into your system.
And since the data is written continuously you can have a RAM based shift register(available with core generator) for carrying the 128 words. ADC data is written into the above said RAM based shift register and data is read from this register to the SRAM.The write clk here is 10 MHz(corresponding to 10 Mega samples per sec) and read clock is also 10 MHz or more (assuming you want to read from shift register without losing any data) .
Here I am assuming that you dont want to use the MSB 6 bits(16-10) of the memory for easier coding.
Input clock, I meant read and write clocks.They have a max value defined for each memory design.Here it wont be a problem.