pierre13
Junior Member level 3
Hello,
I would like to know what are the simulator settings you use for a "memory instance" simulation (transient simu of ~5ns), with just the checking of an output bit, for the sensing operation.
My memory instance is a the smallest instance in terms of bitcells. It means it's "far" below than 1M bits.
Of course there is a "MUX strategy" inside the memory instance, and for the sensing, there is a "sense amplifier + comparator", plus a "biasgen and a clkgen" blocks, and I would say all these three must be simulated at analog point of view.
The simu results, I am checking, are more or less :
-output bit of the comparator
-2 inputs of the sense amplifier (one input coming from the ref and the other from the sensed bitcell)
-clk signals
I am using the following settings :
-ULTRASIM (Cadence) :
usim_opt speed=6
usim_opt sim_mode=a inst= sense_amplifier_block or I can put the three blocks (SA, clkgen, bisagen) as analog. The simu results are almost the same.
-Hsim (SYNOPSYS) :
.param HSIMANALOG=3 so it means for all the blocks
If I set other values, than the default ones, for the parameters : HSIMSPICE and HSIMSPEED, the simu results are garbage.
-HSPICE (SYNOPSYS) :
MAXORD=1 so euler integration method : it happens to simulate once, after some long hours.
My issue, is that I have different results according ot the simulator settings, and I am not sure of which ones are golden.
thanks for any help and have a nice day !
P.
I would like to know what are the simulator settings you use for a "memory instance" simulation (transient simu of ~5ns), with just the checking of an output bit, for the sensing operation.
My memory instance is a the smallest instance in terms of bitcells. It means it's "far" below than 1M bits.
Of course there is a "MUX strategy" inside the memory instance, and for the sensing, there is a "sense amplifier + comparator", plus a "biasgen and a clkgen" blocks, and I would say all these three must be simulated at analog point of view.
The simu results, I am checking, are more or less :
-output bit of the comparator
-2 inputs of the sense amplifier (one input coming from the ref and the other from the sensed bitcell)
-clk signals
I am using the following settings :
-ULTRASIM (Cadence) :
usim_opt speed=6
usim_opt sim_mode=a inst= sense_amplifier_block or I can put the three blocks (SA, clkgen, bisagen) as analog. The simu results are almost the same.
-Hsim (SYNOPSYS) :
.param HSIMANALOG=3 so it means for all the blocks
If I set other values, than the default ones, for the parameters : HSIMSPICE and HSIMSPEED, the simu results are garbage.
-HSPICE (SYNOPSYS) :
MAXORD=1 so euler integration method : it happens to simulate once, after some long hours.
My issue, is that I have different results according ot the simulator settings, and I am not sure of which ones are golden.
thanks for any help and have a nice day !
P.