measurinig offset of a latched comparator

[rivendu]

hi

i am investigating offsets of clocked (latched) comparators. my method is to put a ramp signal at the comparator input from 0 to VDD with a slope of VDD/t_ramp.
t_ramp is the rise time at the input from a pulse source. the comparator is driven with a sampling frequency of 10MHz.
the transistion of a latched comparator is at a time when the clock signal gets high. Thus the comparator is triggered by a rising edge.

is it the right way to measure the offset, which is a typical static characteristic, when i look at the voltage value at the time when the transition occurs and subtract the reference voltage from the measured?

Assuming a reference voltage of 0.5V , the transition is at the rising edge of the clock signal at, let us say, 0.505V. Then the offset voltage is 5mV with a tolerance of deltaV. The deltaV is defined as the voltage difference between the start and the end of a clock period. For t_ramp of 200µs and VDD of 1V we have a slope of m=1V/200µs (of course). A sampling frequency of 10 MHz has a period of 100ns. The deltaV is then 0.1µs * 1000mV/200µs=500µV. The tolerance can be lowered with a slower ramp. The resolution for that offset of 5mV for a comparator with a rail-to-rail ICMR would be ln(1V/5mV)~7 bits. For an ICMR of 0.35 to 1V, this would be ln(0.65V/5mV)~7 bits as well.

do you think the method is right?

 

[pixel]

ok
do you simulate in cadence?

 

[rivendu]

hi,
yes i simulate with cadence , spectre simulator.
do you think it is right?

 

[pixel]

ok, then you can set as x axsis ramp voltage and exactly see at which voltage comparator turns on...
in waveform window plot ramp and comparator output and set x axis to ramp instead to independant variable

 

[n1cm0c]

Offset in a clocked comparator is more complex than that. What you would want to know is the minimum input overdrive that will produce a logic transition within the decision period available.

read this https://www.designers-guide.org/Analysis/comparator.pdf to get a complete picture.

And also this btw https://www.designers-guide.org/Analysis/metastability.pdf

 

[rivendu]

hi
for my work it is important to see, whether the comparator can reach an accuracy of 10 bits. Thus, i set the the speed of the ramp signal and the sampling frequency slow enough that the voltage increase within a clock period is not higher than range/(2^10bits). For a range of 900mV for example, that makes about 1mV. Therefore, if the transition of the comparator occurs one period later than the time when the input voltage exceeds the reference voltage, the comparator has an accuracy of 10 bits. If the transition is later then the accuracy is, of course, lower.

I only would like to know if this is a right method. With an oceanscript i simulate the comparator output versus time for different reference voltages within the ICMR and look up the offset values, slew rate and propagation delay. the slew rate would be between 0.1*vdd and 0.9*vdd. the propagation delay would be at the beginning of the clock pulse and 0.1*vdd.
depending on the highest offset value, i determine the accuracy of the comparator.

i am asking one more time: is this right?