I do not know what would happen if you select "mismatch only" option or if you attach "mismatch block in your model mc file"...............I do not know what would be taking place in the background of the tool that you are using......
If you are going to attach the same model lib file to both the i/p transistors, then there would be no difference in the current between the two transistors.....
The current in the transistor is determined by the model parameters that you are specifying in the model lib file for that particular transistor.......
If you are going to have the same model file for both the transistors, there I would expect the same current on both......You wouldnt see the change......
So try giving different model lib files for the two transistors and you would see different current......
The offset voltage is caused due to mismatch present in the two input transistors......In simulation, this mismatch could be introduced only by giving different model files.....