Mmm... I have never seen this type of naming convention in TSMC 40nm stuffs. However for FDSOI (perhaps for some bulk nodes) libs, the following voltage after the char. voltage could be the back bias (body bias) voltage !
I have worked in some technologies which offer
multiple (but only one at a time, wafer lot wise)
I/O voltages with cell libraries tailored to each,
all bundled in the PDK. The different voltages
mean different thick oxide and different L are
required.
In these cases the supply voltage appears in
the library name and/or cell name to make it
obvious if someone's mixing libraries inappropriately
(like if you see both the 5V and 3.3V libs called out,
better fix it because they can't both be had at once
with only one thick oxide).