Maximum transistor width in 65nm

[fly1]

What can be the maximum transistor width that can be considered in 65nm process for 6T SRAM cell design? The area consideration is also important. So upto what limit can i increase the width of transistor?

 

[dick_freebird]

For any kind of SRAM density you will be nowhere near the
maximum W. Likely the minimum, and a memory designer
will often emply nonstandard layouts for packing reasons.

You can "consider" anything the foundry in question allows
(and some that you might hope to negotiate). But that is
not to say that what you mean to consider, has relevance.

In the core, two contacts per S/D for yield ought to
be as wide as you care about - less, if contact-chain
yields indicate that this is not a significant impactor at
the array size in question. As long as sense line loading
can be swung by the cell drive strength without resetting
the cell, or failing to create enough of a bump for the
sense latch to reliably decide state (mismatch between
sense threshold and precharge levels, perhaps w/ any
settling issues there against desired read cycle time).

So to some extent this question may depend on you
knowing something about your architecture including
estimated layout effects.

But rules, those are unlikely to enter into it.

 

[fly1]

For any kind of SRAM density you will be nowhere near the
maximum W. Likely the minimum, and a memory designer
will often emply nonstandard layouts for packing reasons.

You can "consider" anything the foundry in question allows
(and some that you might hope to negotiate). But that is
not to say that what you mean to consider, has relevance.

In the core, two contacts per S/D for yield ought to
be as wide as you care about - less, if contact-chain
yields indicate that this is not a significant impactor at
the array size in question. As long as sense line loading
can be swung by the cell drive strength without resetting
the cell, or failing to create enough of a bump for the
sense latch to reliably decide state (mismatch between
sense threshold and precharge levels, perhaps w/ any
settling issues there against desired read cycle time).

So to some extent this question may depend on you
knowing something about your architecture including
estimated layout effects.

But rules, those are unlikely to enter into it.

Thank you.