guybrush
Junior Member level 3
maximum capacitor load fpga
Dear all,
I'm designing a memory interface where a lot of memory chip are driven by an FPGA so that the capacitive load on the PCB track becomes high. The effect will be
1) Increase of delay
2) Slow edge on the signal
Can this second effect cause problems? Each input shall have a maximum required transition time but this value is not usually swhon on the datasheet. How can I detemine if buffers are necessary or can be avoided? Using IBIS?
thank you
R.
Dear all,
I'm designing a memory interface where a lot of memory chip are driven by an FPGA so that the capacitive load on the PCB track becomes high. The effect will be
1) Increase of delay
2) Slow edge on the signal
Can this second effect cause problems? Each input shall have a maximum required transition time but this value is not usually swhon on the datasheet. How can I detemine if buffers are necessary or can be avoided? Using IBIS?
thank you
R.