maximum iteration limit in Synopsys

[singla.vishal8]

i got two errors in my design of floating point multiplier

1. Loop exceeded maximum iteration limit. (ELAB-900)
2. it is not reading the main module and sub-modules used in the main module



can anyone help me out....

Thanks
Vishal Singla

 

[TrickyDicky]

If you're getting anywhere near the iteration limit - you have bad code.
post the code and we'll see what we can do.

 

[singla.vishal8]

can u please send me your mail id, so that i can send the code.....

 

[mrflibble]

Or just post your code in the thread. Also see:

If for some reason it's too much code to paste you can put the files in a .zip archive and attach it.

 

[singla.vishal8]

can we talk through mail.... if you say..

 

[TrickyDicky]

No. Please post the code on the forum

 

[singla.vishal8]

module divide_technique_module_call_final_with_cla (a,b,clk,final_result);

input [31:0] a;
input [31:0] b;
input clk;
output[31:0] final_result;
reg [31:0] final_result;
//wire [47:0] final_result;
wire [47:0] final_result1;
wire [47:0] final_result2;
parameter N = 24;
parameter M = 36;
parameter L = 48;
integer h,k;
wire [23:0] a1,b1;
reg [23:0] a3,b3;
reg [23:0] p,q;
reg [47:0] r;
wire one;
wire [11:0] ah,al,bh,bl;
wire sign;
reg sign1;
wire [7:0] m1,m2,m,exp,exp1;
reg [7:0] expo1,expo2;
wire [23:0] a2,b2;
wire [47:0] sum16,sum17,sum18;
wire [48:0] car16,car17,car18;
wire [23:0] result1,result2,result3,result4;
wire [35:0] bresult2,bresult3;
wire [47:0] bresult4;
wire [47:0] aresult1,aresult2,aresult3,aresult4;
genvar i;


assign car16[0] = 1'b0;
assign car17[0] = 1'b0;
assign car18[0] = 1'b0;

always @ (posedge clk)
begin
sign1 = a[31] ^ b[31];
expo1 = a[30:23];
expo2 = b[30:23];
a3 = {1'b1, a[22:0]};
b3 = {1'b1, b[22:0]};
//final_result = final_result2;
final_result = {sign,exp1,r[22:0]};
end


assign sign= sign1;
assign m1 = expo1;
assign m2 = expo2;
assign m = 10000001;
assign exp = m1 + m;
assign exp1 = exp + m2;
assign one = 1;
assign a1 = a3;
assign b1 = b3;


always @ (a1,b1)
begin
p = a1;
q = b1;

for (h=0; h<24 ; h= h+1)
begin
p = p >> 1;
if (p[0] == 1'b1)
h = 24;
end

for (h=0; h<24 ; h= h+1)
begin
q = q >> 1;
if (q[0] == 1'b1)
h = 24;
end

end

assign a2 = p;
assign b2 = q;


assign ah[11:0] = a2[23:12];
assign al[11:0] = a2[11:0];
assign bh[11:0] = b2[23:12];
assign bl[11:0] = b2[11:0];


// First Multiplier

multiplier_wo_clk_with_cla mul0 (al,bl,result1);

// second multiplier


multiplier_wo_clk_with_cla mul1 (al,bh,result2);


// Third Multiplier


multiplier_wo_clk_with_cla mul2 (ah,bl,result3);


// Fourth Multiplier


multiplier_wo_clk_with_cla mul3 (ah,bh,result4);


assign bresult2 = result2 << 12;
assign bresult3 = result3 << 12;
assign bresult4 = result4 << 24;


assign aresult1 = {24'b000000000000000000000000, result1};
assign aresult2 = {12'b000000000000, bresult2};
assign aresult3 = {12'b000000000000, bresult3};
assign aresult4 = bresult4;

generate
for (i=0; i<L; i=i+1)
begin: addbit1
full_adder_wo_clk csa1 (aresult1,aresult2,aresult3,sum16,car16[i+1]);
end
endgenerate

generate
for (i=0; i<L; i=i+1)
begin: addbit2
full_adder_wo_clk csa2 (sum16,car16,aresult4,sum17,car17[i+1]);
end
endgenerate

cla_48 cla0 (sum17,car17,sum18);


assign final_result1 = sum18;


always @ (posedge clk)
begin
r = final_result1;

for (k=48; k>0 ; k= k-1)
begin
r = r << 1;
if (r[47] == 1'b1)
k = -1;
end
end
endmodule

- - - Updated - - -

i have posted my code please check it out..




Thank you

 

[mrflibble]

Please use CODE tags, that makes it easier to read. Also, what do you think the "loop" constructs are going to do? Hint: I am pretty sure that is part of the problem, since the values for a1 and b1 are unknown during synthesis. So it's kind of hard for the synthesis tool to unroll this to any sensible logic.

 

[singla.vishal8]

i have to use that loop, what will u suggest to overcome this problem........

 

[mrflibble]

I suggest you read my comments to overcome this problem. The short version: the loop the way you use it doesn't work. Why not? Because. Please read a textbook on what loop does. I repeat LOOP only works if the synthesizer can decide how to unroll the loop AT SYNTHESIS TIME! So anything that is NOT A CONSTANT is going to fsck you up.

You have non-constant items in there. Ergo, aforementioned fsck you up. Did you read a textbook on "loop" syntax and limitations yet? How about now?




You read it yet?




Now?

Actually it's probably a good idea to kick out loop entirely since apparently you don't quite understand it yet. Can you think of another way to solve it that does not use a loop?