Hi Brad, and thanks for the reply.
While the statement is right in order to avoid the saturation region in a transistor, nevertheless there are cases, like mine, where the transistor bias point is biased at one VCE, and from that point it swings up and down with such an amplitude that it does not enter the saturation region but it does overpass the maximum BVCEO of the device, say, i have a BVCEO of 1.5, a saturation voltage of 150 mV and my transistor is biased at 1 V with a 700 mV swing. It works all the time in the active region but it surpass the maximum stated BVCEO. This behaviour is common in typical advanced SiGe or BiCMOS processes.
The question is then how high is this surpass allowed to be. The ultimate value should be limited by the down level at the transistor saturation voltage, but that does not necessarily means that the transistor will hold all the way up to that swing without degradating or in worst case blowing up because of destructive avalanche effects. I guess that, as long as the impedance at the transistor basis is not an poen circuit, this value will be somewhere between BVCES and BVCEO, being BVCES typically 3 to 4 times higher than BVCEO.
Hope I could made the formulation better and maybe someone can share experience or some interesting documents related to this topic.