Matching Pair for layout design

[izye]

Hi,
For the matching pair in Layout design, I am confused about their size for MN0, MN1 and MN5. Supposed that the matching pair should be in the same size right in the layout design? If their not in the same size, are this design wrong?

Thanks all...

 

[jerryzhao]

Why the bias part consume so much current? and the bias circuit like that cann't supply good current source.
Of course the MN1's Length should better same as MN0 and MN5.

 

[nmmu]

jerryzhao,
why u said that bias circuit the cann't supply good current source?
what parameter we need consider in order to supply good current source?

 

[izye]

Yup..why you said that the bias circuit like that cann't supply good current source.
You means if the transistor have the same length, but different width is okay to apply in the layout design?

 

[jerryzhao]

The bias will change when VDD, corner, temperature and resistor variation.
I don,t know your application, So I cann't comment more about design.Maybe you don't care the bias variation, and the slew rate symmetry.
"but different width is okay to apply in the layout design? "
You can let the width of large MOS and small MOS's ratio is integer. For match the same length is important.

 

[srieda]

Yup..why you said that the bias circuit like that cann't supply good current source.
You means if the transistor have the same length, but different width is okay to apply in the layout design?

The basic principle behind working of current mirror, is that the corresponding gates and sources of the transistors are at the same potential.. ie vgs is same for all of them. then, depending on the ratios of their respective (W/L) ratios, we can mirror different currents into various legs.
While varying (W/L), always vary width and not length... one purpose is matching. But even bigger reason is that the length modulation effect, (bcos of λ), comes into picture and you wont get the exact ratio, even if it is somehow matched...

i also agree with jerryzhao that its a poorly derived current source, but looking at the name of the schematic as chip_test.schematic, i presume this is only for layout practice purposes... if not, I would be interested to know as to why the diff pair is being biased with a low current while the current derived is so high...

hope this helps...

 

[izye]

thanks jerryzhao, thanks srieda..

Actually the circuit is done initially in order to get high gain op amp .
The simulation was okay...However, while doing the layout, I realize there are
some mistake/or not..

However..thanks..maybe I understand a little bit here