Matching and Layout problems !!!

[Harja Alexandru]

Hi,i have a question:
i have 2 transistors (in schermatic w=30u for A and w=30u for B and in layout w=1u).
For common centroid how i must to put them?
i need 30 transistors for A and 30 transistors for B.

i have an idea but i dont now if it is good:
D ABBA ABBA ABBA ABBA ABBA ABBA ABBA A D
D BAAB BAAB BAAB BAAB BAAB BAAB BAAB B D

It is correctly?
Thanks and sorry for my english!

 

[csolis_GT]

The idea of the common centroid is to eliminate the effects of gradients across the two transistors. To minimize the gradient effect you want to use common centroid and have a compact & modular (square) layout. It seems that your idea can work but you might end up with a layout to long in one direction, defeating the purpose of the common centroid. You should try first by using larger w for the layout: 15u, 7.5u, 6u, and you can even combine common centorid with interdigitated fingers. Having a small unit transistors may force to have too much area overhead because of the routing.

Consider your matching requirements, if this a differential pair? current mirror? Based on that evaluate how much of matching techniques you should use.

 

[Harja Alexandru]

The idea of the common centroid is to eliminate the effects of gradients across the two transistors. To minimize the gradient effect you want to use common centroid and have a compact & modular (square) layout. It seems that your idea can work but you might end up with a layout to long in one direction, defeating the purpose of the common centroid. You should try first by using larger w for the layout: 15u, 7.5u, 6u, and you can even combine common centorid with interdigitated fingers. Having a small unit transistors may force to have too much area overhead because of the routing.

Consider your matching requirements, if this a differential pair? current mirror? Based on that evaluate how much of matching techniques you should use.

If i use: ABBA (with w=15u)
BAAB
it is necessary to have left and right dummies?and if it is necessary,dummies must have w=1u or 15u with number of fingers =1?

- - - Updated - - -

Sorry for double post ,for example



dummies's W What size should have? (15u or 1u)
Thanks!

 

[BigBoss]

D ABBA BAAB ABBA BAAB ABBA BAAB A D
D BAAB ABBA BAAB ABBA BAAB ABBA B D

How about this ??

 

[csolis_GT]

Dummies is always recommended on the sides, where the drain and sources are. Since you are not using the devices, they can be thinner compared to the active transistors. There no physics behind my recommendation, but you can use a width size of 1.5x or 2x minimum width for the dummies. I just feel that using the smallest possible width may not protect against edging effects.

 

[jarillak]

Hi...
For better matching, use large active areas for MOSFETs. Since random mismatch is inversely proportional to the square root of MOS active area.So increase MOSFET width from 1u.
Random mismatch=kp/sqrt(WL).

And also try to make the matching as compact as possible.(increase the no. of rows if its not differential)
Finally,there is no any specific rule for dimensions of dummies.

 

[leo_o2]

how about:

D ABBA BAAB ABBA BAAB ABBA D
D BAAB ABBA BAAB ABBA BAAB D
D ABBA BAAB ABBA BAAB ABBA D

 

[Harja Alexandru]

i solved the problem but i have a new problem:

a have 4 transistors A -2 , B-2,C-10, D-2.
it is ok if i make that??

DUMMY CCAABBCC DUMMY
DUMMY CCCCDDCC DUMMY

And i have an other question (see in the picture):

 

[csolis_GT]

I would go with:
X CCAABBCC X
X CCCDDCCC X

since is more symmetric.

As for the second question, since you have the source of the left transistor on a different net, their sources should not be connected. You can do that if both sources are connected to the same net such as ground. In this case when you go from A to B or from B to A, you have to leave some space for their respective sources. What are you planning to connect to S2? The way you have it, you are connecting S2 to ground which is incorrect for the schematic that you have.

 

[Harja Alexandru]

What is wrong here?LVS is not good! see in picture!
why?

 

[Dominik Przyborowski]

What is your LVS error? Some processes doesn't allow to connect bottom plate without via from higher metal

 

[erikl]

What is wrong here?LVS is not good! see in picture!
why?View attachment 112675

I think you have a short circuit between both nodes u1 & u2. Both have RX metal contacts, but these must be separated from each other (if this is really a CMIM, not a POLYCAP)!

 

[hamletboy]

What is wrong here?LVS is not good! see in picture!
why?View attachment 112675

Did you the multiplier were same in sch and layout , Because i saw a 4multiplier in sch ?