Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Thank you guys! All solutions looks valid for me. However, I wonder if I can find more straightforward solution. Can I name the module exactly as the standard cell name? Do you think this will make the synthesis tool use this standard cell for mapping? I am really shocked when I figured out that HDL (VHDL, Verilog) don't have a way to use specific standard cell early in the front end code !!!
But I think its not a good idea to use different std.cells in the design. Because, if most of your blocks are 2v std.cells and one of the module has 5v std.cells, How can you make sure that the right amount of voltage is passing through. Maybe you might not get the correct functionality on silicon. You need to build level shifters to convert 2v to 5v and feed the 5v module and its output should be down converted from 5v to 2v again. Seems to be a hectic task.
what?
you can directly instantiate any cell you want directly in the code. but it won't be RTL anymore, it will be somewhat structural somewhat RTL.
cell_name instance_name (.pin_name(signal), .pin2(signal), ...);
exactly like any other instantiation in verilog: