MAGMA : BUFFER COUNT MINIMIZATION

[praneshcn]

Hi,
Wat are methods which can be used to minimize the buffer count in a design while maintaining timing requirements?



thankz

 

[iwpia50s]

Buffers are added to a design for several reasons:
1) HFN synthesis
2) I/O isolation
3) Logic cell drive strength is too low
4) Wire length is too long
5) Slew violation

Find a way to get around these and you will minimize the buffer count.

 

[santuvlsi]

Hi,
I didnt get ur need.

U r asking hoow to minimise the buffer to while maintanig timing requrinments.

My question is how do u maintain timing requriment without considering buffer?

like to achevie needed timing needed buffer will come, then y u want to minimise it


Santu

 

[praneshcn]

Hi santuvlsi,

I had gone thru some published articles which suggest that the die size is affected drastically in large designs due to buffer count increase. For example, i was working on a design which has 22k gates and 8 macros. after completing the p and r flow, the total buffer count in the design was 4600+. I was just wondering if i could do some things to reduce the buffer count.


(I dont have any hard feelings against buffers)


thankz

 

[santuvlsi]

Dear praneshcn,

Of course friend the buffers size will dramatically increase since what the gate count u obtanied is from front end. but to make the design properly
work without violations,to acheice timing there will be addition of buffers. this we term as backend.

Example Intially there will be 1000 from buffers, but after routing or while tape outing it will be lacs it depends

Santu

 

[vinayshivakumar]

Try bumping up the tau for your library before doing run gate buffer wire. This will reduce the buffer count by forcing the tool to size rather than insert buffers to meet timing. you will have fewer cells but larger ones. This in certain designs helps....