I want to know how to make a marco delay for one cell in the design. I need the clock to read this cell ~0.2ns delayed. I'm using the old CTS in SoC Encounter.
What I found in the manual related to the "Macro delay" is this command:
I create a scheduling file and add the following command to it (I'm not sure I'm setting the values correctly. Should I set the fall delays equal to the rise delays ?.....I need the clock net "clk_i__L5_N837" to be delayed with ~0.2 ns)
Macromodel clk_i__L5_N837 CK 0.3n 0.2n 0 0 0.9497f
and then I set the scheduling file in the configuration file of the tool.
I want to know how to make a marco delay for one cell in the design. I need the clock to read this cell ~0.2ns delayed. I'm using the old CTS in SoC Encounter.
What I found in the manual related to the "Macro delay" is this command:
I create a scheduling file and add the following command to it (I'm not sure I'm setting the values correctly. Should I set the fall delays equal to the rise delays ?.....I need the clock net "clk_i__L5_N837" to be delayed with ~0.2 ns)
Macromodel clk_i__L5_N837 CK 0.3n 0.2n 0 0 0.9497f
and then I set the scheduling file in the configuration file of the tool.
if you need the clock to reach the macro at a specific time, it would be easier to make that delay inside the macro and treat the clock pin like any other clk pin in the system.
useful skew has no relationship to this, it might it even make it harder to be accomplished. optDesign is timing optimization, on its own it will not build the lcock tree for you. you need to use ccopt_design
if you need the clock to reach the macro at a specific time, it would be easier to make that delay inside the macro and treat the clock pin like any other clk pin in the system.
useful skew has no relationship to this, it might it even make it harder to be accomplished. optDesign is timing optimization, on its own it will not build the lcock tree for you. you need to use ccopt_design
I want to create this delay for one of the standards cells in the core so it's not an IP. In this case, should I continue with this command ?
(clk_i__L5_N837 is the clock net of the standard cell that I want it to be delayed and 0.9497f is the input capacitance of this standard cell)
Macromodel clk_i__L5_N837 CK 0.3n 0.2n 0 0 0.9497f
I was able to create this delay by adding 7 extra clock buffers to this clock net "clk_i__L5_N837", however I want to make it automated in the P&R script.
I want to create this delay for one of the standards cells in the core so it's not an IP. In this case, should I continue with this command ?
(clk_i__L5_N837 is the clock net of the standard cell that I want it to be delayed and 0.9497f is the input capacitance of this standard cell)
Macromodel clk_i__L5_N837 CK 0.3n 0.2n 0 0 0.9497f
I was able to create this delay by adding 7 extra clock buffers to this clock net "clk_i__L5_N837", however I want to make it automated in the P&R script.
I can't think of a reason why you would want that behavior for the clock. For data, sure, sometimes you have some weird data dependency. But why force the clock to be delayed?
Be aware that the name clk_i__L5_N837 is not static, it is implementation dependent. If you change anything in your design, or just run clock tree again, the name might change.