aboriginemm
Newbie level 4
Same schematic and same layout, LVS gave me different results.
In the si.out, it said
net-list ambiguities were resolved by random selection
This randome selection sometimes right sometimes wrong.
Will this chip work in reality?
Any one have the same situation before?
In the si.out, it said
net-list ambiguities were resolved by random selection
This randome selection sometimes right sometimes wrong.
Will this chip work in reality?
Any one have the same situation before?