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LVS sometimes successed sometimes failed

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aboriginemm

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Same schematic and same layout, LVS gave me different results.

In the si.out, it said
net-list ambiguities were resolved by random selection

This randome selection sometimes right sometimes wrong.

Will this chip work in reality?

Any one have the same situation before?
 

dick_freebird

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If it can resolve by random selection, it means they
are distinct but topologically the same - for example
a large cascode-stack, where you have paralleled
series FET strings but do not bridge all the center
nodes, drives LVS nuts. They all begin and end at
the same point, but there's too much bookkeeping
in the center with no distinctions to resolve the nets
1:1 to schematic wires, authoritatively.

Sometimes the "problem" can be beyond LVS' ability
(or attention-span, set by coders somewhere) if you
have too many identical-appearing, non-differentiated
nets for it to shuffle. This may require you to modify
your circuit schematic / layout, for example the
"bridging" of distinct but equivalent sub-nodes to get
an easier-to-solve netlist. Not because it is any better
electrically, just in the interest of getting done.

I have seen it many times without ever being hurt.
But I don't understand why you say the selection is
sometimes "wrong".
 

JoannesPaulus

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Add a label in both the schematic and layout to "help" LVS and the ambiguities will vanish..
 

aboriginemm

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JoannesPaulus said:
Add a label in both the schematic and layout to "help" LVS and the ambiguities will vanish..
Thank you. LVS is clean by this way.

Is this the only simulation tools defect? Will real chip recognize the right netlist and work functionally?
 

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