LVS problem: Invalid cell view - 0(unknown)

[arizona999]

tried to use LVS function in c@dence, but did not get through.
The error is as if I can not create the netlisting file from extracted and schematics:

Running artist flat netlisting ...
Warning: Invalid cell view - 0(unknown)

did any body have this problem before? Please tell me how to solve it.

Thanks a lot.

 

[flyankh]

cadence dracula lvs

Why not use DRACULA or other tools?It's a more professional tools than Cadence in LVS.

 

[Serg_SV]

ncsu divadrc.rul

Dracula? Who producer does this soft?

 

[shiowjyh]

Re: Problem of LVS

Guys,
DRACULA is the one you are doing LVS in C@dence...

 

[flyankh]

Problem of LVS

Don't cry,It's my fault.

arizona,have you done it?

 

[arizona999]

Re: Problem of LVS

Don't cry,It's my fault.

arizona,have you done it?

Thanks a lot.

No, I have not solved this problem yet. I just wonder if it is the c@dence configuration problem or my fault.

 

[Hughes]

Problem of LVS

Are you using divaLVS tools? Did you check the CDS_Netlisting_Mode environment variable?

 

[piao]

Problem of LVS

If you use divaLVS, do you have the ivpcell or auLVS and some other cell view for LVS in your corresponding pmos nmos views, there should not only a pmos/nmos symbol and spectre . spice views.

If you generate analog/digital netlist, you should set the CDS_Netlisting_Mode to generate m= or m is not effective.

 

[rajesh13]

Re: Problem of LVS

please check .simrc file in your area. I think you have not listed the view name whose netlist you want to produce.

 

[arizona999]

Problem of LVS

I use layoutPlus to do the layout, I do not know if it is Dracula or davaLVS, who can tell me who to check it out? I am a new learner in this area.

Thanks a lot.

 

[Hughes]

Problem of LVS

Verification tool is different from layout tool. Dracula can run standalone with a GDSII input.

If you are using "Verify / Extract..." and "Verify / LVS..." menus to do LVS, you are using diva.

 

[Question]

Problem of LVS

I can tell you a method, but I am not sure it is useful. First, you simulate your schmatic by spectre. Then change simulater to hspiceS, and ceate a netlist. Then change back the simulater to spectre, and receate the netlist. After do it, you can run your LVS again. good luck!!

 

[dragonwell]

Re: Problem of LVS

I used to have the similar problem. Have set the env variable "CDS_Netlisting_Mode=Analog" already solved the problem. If you are running digital design, set the mode to Digital.

Hopefully can help a little.

Good luck!

 

[Hughes]

Problem of LVS

The words "analog" and "digital" sometimes are confused in terms of divaLVS. In fact, CDS_Netlisting_Mode should be set to Analog if the schematic is built with library analogLib. It should be set to Digital or null string if library sample is used rather than analogLib.

 

[DoctorX]

Re: Problem of LVS

You should first identify to us what "Design Kit" you are using. If you are from university, I assume that you have either NCSU CDK or Cadence PDK. For NCSU CDK, before you get LVS, you should do:

1. run Verify/DRC in Virtuoso. Make sure it is violationfree. Otherwise it won't extract sometimes.
2. Run Extraction.
3. Run LVS. Make sure it is "Schematic against Extracted view", not Schematic against Layout, which is a common mistake. There is no circuit information in Layout view.

For NCSU CDK, three files are essential: divaEXT.rul, divaLVS.rul, divaDRC.rul, all under /local/techfile/. The rule files (if you have not tweaked them) are supposed to be applicable for all technologies, which is of course impossible. Tell me about your design kit, technology, or even tar me your design or a sample design by email, and I can look it over for you.

tried to use LVS function in c@dence, but did not get through.
The error is as if I can not create the netlisting file from extracted and schematics:

Running artist flat netlisting ...
Warning: Invalid cell view - 0(unknown)

did any body have this problem before? Please tell me how to solve it.

Thanks a lot.

 

[zx2051]

Problem of LVS

use dracula ,it is good

 

[Question]

Re: Problem of LVS

If you use divaLVS, do you have the ivpcell or auLVS and some other cell view for LVS in your corresponding pmos nmos views, there should not only a pmos/nmos symbol and spectre . spice views.

If you generate analog/digital netlist, you should set the CDS_Netlisting_Mode to generate m= or m is not effective.

OK, I know it. It is the problem, thanks.

 

[Teddy]

Re: Problem of LVS

Well I guess it is about year too late but check the view list and a stop view