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lvs errors - property errors, incorrect instances - why?

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okjtech

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lvs errors

I am currently in doing layout, using standard cells from the fab. The circuit is pretty simple using flip flops and muxs. I used cadence chip assembly router to route most of the circuit. I added nwell and substrate contacts for vdd and vss respectively. When I run lvs it doesnt pass, i get a few property errors, as well as incorrect instances. I just added the nwell and substrate contacts to the top level of the circuit and connected on vdd and vss pin to the contacts, since vdd and vss are connected throughout the circuit. I was wondering if this is incorrect? Also, what could be other possible reasons for these lvs errors?
 

lvs errors

i guess that your instances added by the nw region have different potential each other. u can assure that from the relative schematics. In addition, what body silicon process u are using?
 
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