Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

lvs errors - property errors, incorrect instances - why?

Status
Not open for further replies.

okjtech

Newbie level 1
Joined
Aug 28, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,290
lvs errors

I am currently in doing layout, using standard cells from the fab. The circuit is pretty simple using flip flops and muxs. I used cadence chip assembly router to route most of the circuit. I added nwell and substrate contacts for vdd and vss respectively. When I run lvs it doesnt pass, i get a few property errors, as well as incorrect instances. I just added the nwell and substrate contacts to the top level of the circuit and connected on vdd and vss pin to the contacts, since vdd and vss are connected throughout the circuit. I was wondering if this is incorrect? Also, what could be other possible reasons for these lvs errors?
 

ksj116

Newbie level 6
Joined
Nov 27, 2007
Messages
12
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,281
Location
China
Activity points
1,336
lvs errors

i guess that your instances added by the nw region have different potential each other. u can assure that from the relative schematics. In addition, what body silicon process u are using?
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top