LVPECL to LVDS termination.

[Rahul Soni]

This is the standard to convert LVPECL to LVDS termination. I am confused here to see the voltage divider of 10k and 10k only on one line.

Shouldn't this divider be present on the upper line also?

Thanks in advance.

 

[kemiyun]

That 100 ohm between to terminals provide DC bias to each node. So there is no need. You can put if you want but if there's mismatch between them you'd burn unnecessary power.

If you look at the document, there is always to bias networks if there is no termination, but always a single one if there is termination.

But don't take it from me, simulate.

 

[Rahul Soni]

That 100 ohm between to terminals provide DC bias to each node. So there is no need. You can put if you want but if there's mismatch between them you'd burn unnecessary power.

The 100 ohm resistor will generate the 350mV at its terminals. (Since, in LVDS we have a 3.5mA current source.) Now to make the common mode voltage same of both (LVDS and LVPECL) we are using a resistor divider. According to this, i'll get the appropriate common mode voltage on second line .. But I don't think that i'll work for the first line.

You got what I am saying ?

 

[kemiyun]

Dude, I completely understand what you're saying, I designed an LVDS interface circuit myself I'm familiar with it a little bit.

Imagine a situation where you have two 50 ohms and put the common mode bias at the center of it. This is the best case scenario, and it definitely would provide necessary bias to each node, since there is no DC current flowing to the LVDS receiver.

But this is not the scenario you'd usually get because 100 ohm is usually there and you have no means to divide it. Assume no signal is present and the circuit in the document is used, wouldn't both nodes be at the same voltage which is the bias voltage in this case? There is no current flowing anywhere except for the DC current through the bias network and even though it's through a 100 ohm there is still a path from one side to the other and since no current is flowing through it voltage drop across that 100 ohm is 0. So both ends would be at the same voltage for DC.

When there is signal on the line it's going to disturb the balance and yes there's going to be some amount of error caused by this but probably not that much. So yeah, that circuit provides DC operating point to both lines. I'd choose 50-50 ohms + resistor bias if I was given a choice, but this would work too.

If you put two biasing networks on each side, in the case of a mismatch, certain amount of current is going to flow through 100 ohm resistor and plus you're going to have higher power consumption on biasing network because you're using two of them.

Since I was talking from my own experience, and I don't trust myself, here find the same things I said from a different source:

**broken link removed**

It's from sitime, they're not that great but finding quality documents about LVDS was always a troublesome process. Your interest is fig 20. and its explanations.

 

[FvM]

Now to make the common mode voltage same of both (LVDS and LVPECL) we are using a resistor divider.

No. To make both common mode voltages equal, you would just omit the capacitors. ECL and LVDS I/O standards have different common mode voltage, that's why the capacitors and the bias network are used.

Kemiyun has explained the working of the bias network in detail, I have nothing to add substantially, except for one point. Although the LVDS receiver is perfectly biased, a high speed circuit designer would possibly avoid this component placement because the parasitic resistor capacitance adds an asymmetrical load at high signal frequencies. More a matter of high speed design look and feel than a real problem unless you are going to high GHz signal rates.