LVDS supply requirements

[snaku]

Hi All,

In our design, we have an ADC which gives out differential parallel outputs.The ADC operates at 3.3V. The differential output is interfaced to FPGA, which operates at 2.5V.

Is it necessary that both transmitter and receiver should be at the same voltage levels?

Thanks & Regards,
Naveen

 

[FvM]

No. LVDS IO-standard uses the same signal level independant of supply voltage of the respective chip, ususally something between 1.8 and 3.3V.