LVDS reciever from Bonis paper

[rivercam]

Hi,
i wish to design LVDS recievr in 350nm technology and got the paper from IEEE by boni. It seems that lot of peple in this forum discussed the same paper many times. As a first start for the same spec in the paper for reciver design can some one tell me how to find aspect ratio of devices?

Well, even some one tell me how to start design from the spec? Iam particularly not getting the design of second stage(Latch) in that paper and the device sizes for cross coupled pair and diode connected transistors. Also wondering how to size up the output stgae current starving inverters.

I request you to please give me an hint how to do this, so that i can start something and can go for something interesting.

Thanks in advance

 

[adsl]

Hi,
i wish to design LVDS recievr in 350nm technology and got the paper from IEEE by boni.

Are you talking about this one: "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS"?

 

[rivercam]

Hi ADSL,
yes. Iam talking about the same one you mentioned. could you please guide me about how to start design for the same spec mentioned in the paper.

Thank you

 

[rivercam]

Hi,
can some one help me to design the reciever for LVDS in 350nm technology.
I wish to first start from the design mentioned in the following paper.

"LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS"

i would like the design process for the given spec, say the same spec in that paper.

especially i need help in finding w/l sizes and resistor values of the opamp and latch. If you need paper i can send to yur email or you can find that one in the google for free.

Thanks in advance

 

[roadway]

Rivercam, have you ever got what you need?