LVDS as Window Comparator

[Sara92]

Dear all,

Please don't burst out laughing - well you may of course... 8-O
Again one of those silly questions:
Would it be possible to use/abuse a LVDS receiver as window comparator? Basically I need to analyze a signal and decide whether I have high (>100mV), low (<100mV), or something in between. I realized that comparators with sufficient speed (400MHz) are a bit expensive, but could I use a LVDS receiver instead? Impedance matching would be no problem for me. I'm more worried about the stability of the 100mV thresholds. How would they behave over temperature and from part to part?

Thanks so much for answering anyway
:lol:

 

[milind.a.kulkarni]

Hi Sara92,

As I know LVDS is a digital interface differential current based interface.... the direction of current accross the differential resistor decide zero or one ...... Also LVDS has it's own standards like LVDS2.5 or LVDS3.3 etc..... Basically the digital information ( bit stream zeros and one) are transmitted using polarity inversion concept meaning ....if you take LVDS2.5 with single channel (Ch1+ and Ch1-) and clock (CLK+ and CLK-) for an example..... if your digital message on the LVDS channel 1 to be send is let say 1,0,1,0 then following things happens -
for 1 is there then Ch+ will go high and Ch- will go low now at the receiver side the polarity will be (Ch1+) - (Ch1-) is positive....
for 0 then Ch+ will go low and Ch- will go high now at the receiver side the polarity will be (Ch1+) - (Ch1-) is negative....
Also Ch+ and Ch- are shifted on certain bias voltage for an example on LVDS2.5 the voltage is 1.25v bias voltage.... and these zeros and ones are sampled using LVDS clock

The difference between two Ch+ and Ch - is max 400 mili-volts.....

As I read your post I think you are having two state >100mv and <100mv ....... I am not sure how you will use the LVDS for this kind of analog signal detection.....I am not able to catch your idea there ?

Please refer chapter-1 for more info-

https://www.pa.msu.edu/hep/d0/ftp/r...t_information/national_lvds_owners_manual.pdf

Good Luck

 

[FvM]

I hear a possible misunderstanding from your post. The Vith+ and Vith- specifications of LVDS receivers don't involve a hysteresis or something like a window comparator. Typically, the receiver will show a threshold around 0 for both edges.

As every min/max specifications, the Vith numbers are just guaranteed limit values. You may read it as a maximum threshold offset specification, so very clearly, LVDS receivers aren't accurate enough for your intended purpose.

 

[Venkadesh_M]

I think you need a window comparator for highly varying input signal, am I right??
and did you mean a comparator like this ???

**broken link removed**

can you elaborate on the signal which is going to be monitored...

 

[Sara92]

Guys, you are fast!
Okay sorry I should have been more specific:
I need to detect three states
>100mV = +1
<100mV =-1
Zero =0

I was hoping to use two LVDS receivers in parallel, with polarity of inputs changed on number two.
The resulting ouputs of the two receivers I would analysze with a simple logic to deduce the desired states.

LVDS1 LVDS2 OUT
high low +1
low high -1
low low 0

Does this make sense????
Thanks, Sara

 

[Venkadesh_M]

this makes sense but did you notice the post #3 and also lets compensate it with a additional source in series..
and one more question what do you mean 0 ?? is 0.00001V is a 0? then what is the thresold level for 0?

 

[milind.a.kulkarni]

Hi Sara92,

So you want to detect three states +1 , 0 and -1 using standard LVDS receiver..... I think it is not possible as standard LVDS receiver..... as there is not case like 'low low 0' on Ch+ and Ch- for data transfer and detection of LVDS......LVDS receiver output you will get in the digital form like 0 (zero) or 1 (one)......


I think @Venkadesh_M post-1 approach of using OPAMP is better.... but only that you need to think is what is the frequency of such signal.....if you have very high frequency like in Gigahertz it will require special design.....

Good Luck

 

[Sara92]

Hi,
let's call the three states A, B, and C :-D
A for >+100mV
B for "noise level"
C for <-100mV

sorry, the formating was poor in my previous post:

output limiter1=high + output limiter2=low equals state A
output limiter1=low + output limiter2=high equals state C
output limiter1=low + output limiter2=low equals state B

Cheers!

 

[Venkadesh_M]

I think the source shd also support that much frequency.......

- - - Updated - - -

but i did this for the first case........

- - - Updated - - -

There may be small changes but can be done.....

 

[Sara92]

Oh well, right, post No 3

Hm, does this mean I should use single ended signal and "compare" it to a reference voltage of 100mV on the LVDS input?
And the receiver can have any offset threshold between 0-100mv? :|

 

[Venkadesh_M]

no it means it is not destined for that it may not doing it preciously or there may not a exact thresold.......

 

[Sara92]

Okay, I guess this settles it...

Thanks a lot!