In a design with LVDS signals (e.g. 400 - 800 Mbps speed), we have matched impedance differential pair rules both for outer and inner layers. Vias act as capacitive stubs, but they typically don't cause problems at sub-Gbps speed. At higher frequencies (e.g. SATA, USB3, PCIe), via backdrilling may be used to reduce parasitic capacitive load.
I see a possible problem in your stackup with the two adjacent signal layers. The scheme causes crosstalk and impedance variations depending on the interaction of differential pairs on both layers. It can work if you strictly avoid vertically parallel traces and restrict the number of crossings.