LUT utilization is 107%!!! How can I reduce that ?

[omara007]

Hi guys ..


I'm trying to synthesize my VHDL design using XST and it's taking forever, i.e. it never completes synthesis up to the generation of the netlist .. for that, I decided to try Synplify (ver. 2009.6SP1) .. it took around 30 mins to complete the synthesis .. but the LUT utilization is too high .. 107%!!!! .. i.e., the design won't fit in the device .. I tried to map this netlist and, as expected, it didn't map as the utilization is more than 100% ..

There is another problem that I'm using an IP whose utilization doesn't show up during synthesis .. for that I even want to optimize my design to maybe 75% or even less to leave some space for the IP as well ..

Is there any way to optimize the number of mapped LUTs ? .. can I map them to the unused RAM blocks? .. given that I didn't use any BRAM or DRAM in my design ..

P.S. my target device is Spartan-3A DSP 1800A .. and I'm using ISE 11.2

 

[vipinlal]

If you are using functions with loop instructions then try to remove such functions and make them clock controlled.For example say you have a function with a loop( of 50 times) then the statement executed inside loop is replicated 50 times in hardware.To avoid this use clocked calculation.But the disadvantage is that this will require 50 clock cycles for the output to come.

--vipin
https://vhdlguru.blogspot.com/

 

[omara007]

Unfortunately, this is not the case ..

 

[sameh_yassin99]

Hello there,
I had a similar problem while implementing channel encoder/decoder, I did the following:

1- I removed some code generated by Matlab and made it simpler logic, I had to rethink about how to generate a raised cosine signal.
2- I set the XST optimization effort to "Area"
3- I tried to give location constraint for IP, it didn't help but it almost did I think you should try it.

The main thing is that you have to change some parts of your code...

regards

 

[omara007]

Hello there,
I had a similar problem while implementing channel encoder/decoder, I did the following:

1- I removed some code generated by Matlab and made it simpler logic, I had to rethink about how to generate a raised cosine signal.
2- I set the XST optimization effort to "Area"
3- I tried to give location constraint for IP, it didn't help but it almost did I think you should try it.

The main thing is that you have to change some parts of your code...

regards

Hi Sameh

My RTL code is not generated from a matlab high level code like yours .. I have already coded everything in terms of FSMs .. and arithmetic units .. for that, it's really hard to change any part of the code ..

The XST is not completing the synthesis run with me .. it takes up to 8 hours in optimizing one of my blocks after finishing the advanced HDL synthesis .. hence, I stop it manually.

I have already sat my optimization goal to area instead of speed .. increased the fanout limit .. selected to map excess LUTs to unused BRAM .. selected the FSM implementation to Gray and BRAM .. etc. But I didn't anchor any block to a specific location on the chip as I couldn't even pass the synthesis step using XST !!


Sameh .. would u please tell me where do u work ?

 

[pmat]

Hi,
i think that the key for the area reduction for your project is to carefully identify
inputs in your design which should be stuck in a specific value or outputs which
are not needed. If you can identify any of these two cases, the logic cones which
are driven by this input or the logic cones which drive only this output will be
optimized, if not removed. If you cannot identify any of these, break the project
into blocks and do the same for the biggest ones.
The chain effect of removing useless outputs or stuck-at inputs reduces the area
a lot. There are many things you can try on your own...

Pavlos