LUT RAMS--virtex4 how to implement

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chaitu2k

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ram_style=distributed

hi all

i want to implement 16 bit and 28 bit wide memory using LUT RAM...i dont want to use BLOCK RAM using core generator.....

can anyone tell me how or forward some document which gives an insight on how to do so...

cheers
 

Search the Xilinx Constraints Guide for RAM_STYLE DISTRIBUTED.

Here's a Verilog example:
reg [27:0] myram [0:15]; // synthesis attribute RAM_STYLE myram "DISTRIBUTED";

Good luck!
 

Just select the appropriate CoreGen module...

Distributed Memory v7.1

Data sheet: DS230 January 18, 2005
 

hello,
u must see "xilinx language template" and there u find how to implement distributed RAM and BLOCK RAM
 

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