LUP.2 DRC in TSMC 28nm Technology

[ravikiran1550]

Hi all,

can you help on LUP.2 violations coming top of the CLAM cells. which are placed for ESD protection in the CHIP. i am getting LUP.2 Violation in the fullchip. fullchip has 10 macrons and it is coming from the one macro. and the macro has analog IP which is provided by the client. we tried removed all the power hooked to the macro but no luck, when we remove the signals Errors gone. but we have 250 pin are hooked up. how to find what is the issue is causing LUP.2. here i am attached screenshot.

 

[npardeepsain]

You can use some debugging setting from the foundry runset to identify the OD injector and then move those clamps cells away from the OD injectors.

Please check the definition of I/O signal pad. Once you remove the Signals pad names from the design then tool will not find the OD injector and that may be the reason you are not seeing the fails after removing the nets.