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@ltera Max II and Quartus - help with tools needed!

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ted

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Hi,

I am using the free versions of @ltera Max II plus and working on a design for ACEX1K50. The design fits nicely with plenty of free resources. Timing is bit though in several places, so I am only conserned of timing, not area.

The project is written in VHDL, and therefore I have only restricted control on what is really generated (by Leonardo Specrum in the first place).

However, the fitter in MAX II plus does place everything directly stupid places, often maximising the delay. Of course, I can fix it to some degree in the floorplan editor, but when using so-called Quartus fitter option, one can not fix placement on cell/LUT level. Are there any descent ways to control the fitter and get the chip peform to it's best? Does Quartus maybe do better job and allow better manual control?

Another issue is fanouts. It seems that on ACEX1K a fanout of maybe up to 6-8 is pretty fast, but on greater fanout it is rapidly getting very slow. Due to high abstraction in VHDL there is no easy way I know of to force generating parallel (redundant) logic, so that fanout is kept on low enough level for the individual cells to speed up the logic.

Any good ideas, anybody?
 

ngjh

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If you want to generate redundant logic always, I think the only way to tell the synthesizer to do so using LCELL primitives. However, this will make the code less portable.

Method (assume signal 'original' needs to be duplicated):

library altera;
use altera.all; (not 100% sure if this is correct)

LC1: LCELL port map (original, orig_dup1);
LC2: LCELL port map (original, orig_dup2);
....


Hope this will help[/i]
 

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