LTC2440 Problem: SDO Output Always Logic High

[salihonur]

Hi,
I have a strange problem about LTC2440. Proteus simulation runs perfect, but the SDO pin of ltc2440 gives always logic high at real circuit. I watch the waveform on the scope and see same as this (Note: I draw short form of the wave 4 clock pulses instead of 8 bit).

SDO ___-------------------------------------------------____

SCK _____-_-_-_-___-_-_-_-___-_-_-_-___-_-_-_-__________ (actually 8 pulses in each clock group)

CS --________________________________________----------

I think the problem is about physical. I have added the schematic and source code. How can I fix this problem?

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Code C - [expand]
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#include <18F2520.h>
#device *=16
#fuses INTRC_IO,NOWDT,NOMCLR,PUT,PROTECT,CPB,NOBROWNOUT
 
#use delay(clock=32000000,restart_wdt)
#use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8)
 
//#fuses INTRC_IO,NOMCLR,WDT,WDT64,NOBROWNOUT,PUT,NOLVP,CPB,CPD,PROTECT,NOWRT
 
// Port ve Pin Tanımlamaları ===================================================
#define     ADC_CS_     PIN_C2          
#define     BUSY        PIN_C1
 
#byte   PORTA           = 0xF80
#byte   PORTB           = 0xF81
#byte   PORTC           = 0xF82
#byte   TRISA           = 0xF92
#byte   TRISB           = 0xF93
#byte   TRISC           = 0xF94
 
#byte   SSPSTAT         = 0xFC7
#byte   SSPCON1         = 0xFC6
 
#bit    CKE             = SSPSTAT.6 
#bit    CKP             = SSPCON1.4 
 
#bit    LTC_BUSY        = PORTC.1
#bit    LTC_CS          = PORTC.2
#bit    LTC_SCK         = PORTC.3
#bit    LTC_SDO         = PORTC.4
#bit    LTC_SDI         = PORTC.5
 
#bit    BT_SET_OFFSET   = PORTC.0
#bit    BT_SET_REF      = PORTC.6
 
#bit    OFFSET_SETTING  = PORTA.3
#bit    ILETISIM_LED    = PORTB.3
//==============================================================================
#bit    IA4421_SDI      = PORTA.1
#bit    IA4421_SDO      = PORTA.7 //0
#bit    IA4421_SCK      = PORTA.2
#bit    IA4421_NSEL     = PORTA.5
#bit    IA4421_NFFS     = PORTA.6 //3
#bit    IA4421_NFFS_D   = TRISA.6 //3
#bit    IA4421_NIRQ     = PORTA.4
//===========================================================================
 
int TxPacket[10],RxPacket[10],Paket[80],ALICI_ID_H,ALICI_ID_L,VERICI_ID_H,VERICI_ID_L,LOAD_KG_8L,LOAD_KG_8H;
int16 Frequency_cmd,Transmitter_control_cmd,Data_rate_cmd;
 
//-------------------------------------------------------
#define EPROM_OFFSET_ADDRESS        0x00
#define EPROM_REF_POINT_ADDRESS     0x04
#define EPROM_REF_VALUE_ADDRESS     0x09
//-------------------------------------------------------
 
float data,calc;
int32 offset, ref_adc, ref_kg, load_kg;
 
struct fourbytes 
{ 
    int8 d0; 
    int8 d1; 
    int8 d2; 
    int8 d3; 
}; 
 
union
{
    signed int32 bits32;
    struct fourbytes by;
} load;
 
//-------------------------------------------------------
 
 
#include <math.h>
#include <stdio.h>
 
#define RF_CHANNEL  39
#define ID_HIGH     14
#define ID_LOW      14
 
#include <IA4421_4th_GENERATION.h>
//===========================================================================
 
//===========================================================================
// MAIN Routine 
void main(void)
{
    int16 i,RF_Tolerans;
    //---------------------------------------------------------------------------
    setup_oscillator(OSC_32MHZ);
    restart_wdt();
    
    set_tris_a(0x5B);
    set_tris_b(0x61);
    set_tris_c(0x02); //14
    
    
    
    PORTA=0;
    PORTB=0;
    PORTC=0;
    
    
    output_high(ADC_CS_);
    setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED);
    CKP = 0; // Set up clock edges - clock idles low, data changes on
    CKE = 1; // falling edges, valid on rising edges.
 
 
    enable_interrupts(global);
    restart_wdt();
 
 
    
    IA4421_init(RF_CHANNEL,7);
    Set_RF_Rx();
    restart_wdt();
    
    delay_ms(100);
    restart_wdt();
    
    
    VERICI_ID_H = ID_HIGH;
    VERICI_ID_L = ID_LOW;
    ALICI_ID_H = VERICI_ID_H;
    ALICI_ID_L = VERICI_ID_L;
    
    IA4421_init(RF_CHANNEL,7);
    Set_RF_Rx();
    
    while(1) 
    {
        i++;
        if(RF_Tolerans<250)
            RF_Tolerans++;
            
        if(RF_Tolerans>249 && !Receive_Packet())
        {
            ILETISIM_LED=(i/1000)%2;
            
            load_kg=0;
            
//          output_low(ADC_CS_);
            
            LTC_CS=0;
 
            load.by.d3 = spi_read(0x78);
            load.by.d2 = spi_read(0x78);
            load.by.d1 = spi_read(0x78);
            load.by.d0 = spi_read(0x78);
            
            LTC_CS=1;
            
//          output_high(ADC_CS_);
            
            // Subtract offset (result is in 2’s complement)
            load.bits32 = load.bits32 - 0x20000000;
            data = (float) load.bits32; // cast as float
            
//          calc=((data-offset)*max_kg)/(max_adc-offset);
            calc=ref_kg*(data-offset)/(ref_adc-offset);
            load_kg=load.bits32;
//          load_kg=calc;
            
            
//          LOAD_KG = 1000;
 
 
            LOAD_KG_8L=make8(LOAD_KG,0);
            LOAD_KG_8H=make8(LOAD_KG,1);
            restart_wdt();
        }
 
        if(Receive_Packet())
        {
            RF_Tolerans=0;
            ILETISIM_LED=!ILETISIM_LED;
            
            if(RxPacket[4]==0x07)
            {
                Set_RF_Tx();
                restart_wdt();
                TxPacket[4] = 0x06;                          // KOMUT
                TxPacket[5] = LOAD_KG_8L;                    // BİLGİ
                TxPacket[6] = LOAD_KG_8H;                    // BİLGİ
                TxPacket[7] = make8(LOAD_KG,2);                 // BİLGİ
                TxPacket[8] = make8(LOAD_KG,3);                 // BİLGİ
                TxPacket[9] = CALCULATE_CRC(TxPacket,9);     // CRC
                Send_Data(10);
                restart_wdt();
                Set_RF_Rx();
                restart_wdt();
            }
 
        }
        
        restart_wdt();
    }//end of while 
}   
//===========================================================================

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[mister_rf]

Maybe because setting Serial Data Input= ''1''?

This pin is used to select he speed/resolution of the converter. If SDI is grounded (pin compatible with LTC2410) the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nVRMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate.

http://cds.linear.com/docs/Datasheet/2440fd.pdf

 

[salihonur]

No change. But sometimes it give different values rondomly. I wonder if the problem is caused by PIC frequency. May it possible?
I had connected SDI pin to PIC and same problem was happened.

 

[salihonur]

I tied SDI pin to GND and i read the values every 20 loop period. However data is like rondom. What can i do more?

 

[mister_rf]

The converter is in external SCK mode, what’s the frequency of the clock signal driving SCK during the data output?

 

[salihonur]

The frequency of SCK is 2 MHz.

The problem is shown in the picture. All things are on same position. But adc sends data like randomly.



Each groups are zoomed:

 

[mister_rf]

For the LT2440:

the speed change from 6.9Hz to 880Hz is implemented by simply driving the SDI pin from low to high. Alternatively, the speed can be increased in nine steps (5-bit input to SDI) from 6.9Hz to 3.5kHz

.
Maximum up to 3.5kHz Output Rate so just try to display the raw value received from the ADC as a 32-bit hex value every 500 ms.
SDI pin = low, > SCK = 6.9Hz
SDI pin = high > SCK = 880Hz

https://cds.linear.com/docs/Application Note/an96fa.pdf
https://cds.linear.com/docs/LT Journal/LTC2440_Mar03.pdf

If you are using external SCK (generated by the microcontroller) the EXT pin is tied low for this mode, so in this case BUSY signal is not used for your design.

 

[salihonur]

Hi again. I have changed the circuit and the software in accordance with the product datasheet. EOC is checked every 32 bit spi reading if conversion is active. The BUSY interrupt gets logic high after the last SCK clock. (External SCK and single conversion, 3 wire SPI)

All pictures show the same reading action (both Vin- and Vin+ pins are connected to GND). SDO output waveform are still different. And EOC=0 in all reading action as well.

I'm still in trouble

Preferences like this:

OSC Frequency = 32 MHz
Timer 2 = 508.13 Hz setup_timer_2(T2_DIV_BY_16,82,12); // timer is 508.13 Hz
SCK is generated by timer2 setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_T2|SPI_SS_DISABLED);

 

[mister_rf]

And for the new circuit SDI pin level high? (SCK = 880Hz)

 

[salihonur]

SDI is connected to GND, so conversion rate is 880 hz. Do I have to set the timer2 for 880 hz or above (for ex. 886 hz)?

 

[mister_rf]

If SDI=GND conversion rate =6.9Hz. Need to connect SDI to ''High''.

 

[salihonur]

No change. Still I receive unstable data.