STM32F3 Timer1 negative output delay?

[Jadeit]

Timers in the STM32F3 processor have TIMx_CH1 and TIMx_CH1n outputs
I have simple questions.
Is there a negative output from the same source as a positive one by inserting the inverter or not?
In other words, are the negative and positive output of the reference clock synchronous or is there some shift caused by the inverter and If so how big is it?

 

[FvM]

The usual application involves an intentional delay between both outputs. With delay set to zero, I would expect both outputs to be set simultaneously. Consider that outputs are registered after all logic.

 

[danadakk]

Might be prudent to use a scope and look. I would agree with FvM but could find no reference in datasheet.
The deadtime generator seems to support one clock, which would make me think its registered, but never
hurts to check. If using ext clk res time is ~ 14 nS at 72 Mhz clk, so if it was a gate delay, not registered,
worst would be ~ 7 nS (144 Mhz clk ref in datasheet). Then layout becomes a a factor.

If you do the check make sure you have set deadtime and clk right before looking. Hopefully you are
not trying to depend on a max delta in the sinflge digits kinds of speed as T & V effects would blowup your goals.


Regards, Dana.