Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Lower transistion limits for CTS?

Status
Not open for further replies.

avinashsiva21

Newbie level 2
Joined
Jun 5, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
Why do we set lower transition values while building clock tree compared to signal nets transition limits?
Thanks
 

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
110
Trophy points
1,323
Location
Bangalore,India
Activity points
4,676
Do you mean the Sharp transition?

For example, data will have 400ps tran limit, but the clock may have 150ps tran limit. Am I right?
 

avinashsiva21

Newbie level 2
Joined
Jun 5, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
Do you mean the Sharp transition?

For example, data will have 400ps tran limit, but the clock may have 150ps tran limit. Am I right?

Yes Kumar, why do constraint steeper trans limits for Clock signals and why dont we use the same values for data paths aswell?
Thanks
 

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
110
Trophy points
1,323
Location
Bangalore,India
Activity points
4,676
There are 2 reasons for having sharper transition on clock path.
1. To avoid min pulse width issues.
2. To avoid Cross-talk issues ( Crosstalk impact will be more if the transition is too bad ).
 

artmalik

Full Member level 5
Joined
Mar 13, 2013
Messages
255
Helped
89
Reputation
178
Reaction score
87
Trophy points
1,308
Location
San Diego
Activity points
2,997
The clocks need to have good transition time because variation. Have a sloppy transition time means the cells chosen in the design will be weaker and will have more variation due to PVT. Also Jitter and Duty cycle distortion in the clock will be more because of weaker cells. All these tend to reduce the max frequency at which the design can work . One of the goals is to achieve higher speed.
Data path is bound between two edges ....and one path may not be effected by the other. The timing is met by upsizing the gates......
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top