Lower transistion limits for CTS?

[avinashsiva21]

Why do we set lower transition values while building clock tree compared to signal nets transition limits?
Thanks

 

[kumar_eee]

Do you mean the Sharp transition?

For example, data will have 400ps tran limit, but the clock may have 150ps tran limit. Am I right?

 

[avinashsiva21]

Do you mean the Sharp transition?

For example, data will have 400ps tran limit, but the clock may have 150ps tran limit. Am I right?

Yes Kumar, why do constraint steeper trans limits for Clock signals and why dont we use the same values for data paths aswell?
Thanks

 

[kumar_eee]

There are 2 reasons for having sharper transition on clock path.
1. To avoid min pulse width issues.
2. To avoid Cross-talk issues ( Crosstalk impact will be more if the transition is too bad ).

 

[artmalik]

The clocks need to have good transition time because variation. Have a sloppy transition time means the cells chosen in the design will be weaker and will have more variation due to PVT. Also Jitter and Duty cycle distortion in the clock will be more because of weaker cells. All these tend to reduce the max frequency at which the design can work . One of the goals is to achieve higher speed.
Data path is bound between two edges ....and one path may not be effected by the other. The timing is met by upsizing the gates......