Re: Low-power design
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Sesson 2: How to reduce power consumption
Now, we continue to the next topic "how to reduce power consumption". There are a lot of techniques and different methods attack different portions of the power equation. They usually have some overhead of some sort. For your knowledge, I will point these techniques to kind of power-consumption that it saved.
Clock gating - dynamic power reducing technique
The oldest and most tried-and-true technique for reducing power is clock gating. More than 1/3 of an IC design’s dynamic power is in the chip’s clock-distribution system.
It’s a pretty simple concept: If you don’t need a clock running, shut it down. You would use the enable signal that controls the multiplexer to control the clock cell to clock the signal off. Because, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. It's free to save 20-30 percent of dynamic power consumption for sequential blocks.
Multivoltage design (M-Vdd) - dynamic-power reducing
Multivoltage design enables designers to give the critical paths and blocks in their designs access to maximum voltage for the process and specification, but the designers then reduce the voltage for less power-hungry blocks.
For example, a processor block may require a clock speed of 1.0 GHz, but a USB core may require only 30 MHz to comply with the USB protocol and thus require less voltage to run. So, if designers give the USB core only the power it needs, they can drastically reduce the overall power the design consumes.
Designers also put level-shifters between blocks that are running at different voltages and can use isolation cells to shut-down any voltage-domain is we don't need it run. Multivoltage design have many way to save your chip power consumption: multi voltage islands (w/ OR w/o shutdown mode), voltage scaling that have included voltage regulator and mode control sub-blocks into main-block.
Power-savvy memory - both dynamic and static power consumption
This is another popular technique for lowering both dynamic power and leakage is to use power-aware memories. In its simplest form, the technique involves shutting down segments of a memory array when they are not in use. Another technique in this category is body-biasing memories. In this method, designers reverse-bias a memory when it is not in use, which essentially raises the threshold voltage and in turn slows leakage.
Another technique gaining popularity is to use multimode power for memories. In this technique, designers employ memory with several power modes. Many designs employ dual-function memories so that, when the CPU accesses a memory to read or write data to run a main application, the memory receives full access to power to perform the operation. However, when the memory is not required to read or write, designers can program the memory to power down to a level at which the memory gets only enough power to retain its memory content.
Multithreshold design (M-Vth) - Static power reducing technique
About five years ago, when excessive power consumption became a problem, foundries started to offer multi-threshold voltage libraries for low-power and high-speed design. Multiple-cell libraries help designers deal with both leakage and dynamic power. A multicell library typically comprises at least two sets of identical cells that have different threshold voltages. Those with higher threshold voltage are slower but have less leakage; conversely, the cells with lower threshold voltage are faster but leak. The high-threshold-voltage cell typically has 50% less leakage than a low-threshold-voltage cell with no bad side effects, such as area gain.
To deal with leakage power using multiple types of cells, designers today employ multithreshold design. You can use high-speed cell (higher leakage) for speed-critical paths, and, use lower-speed cell for non-critical paths if you want to reduce the leakage. You also trade-off between die-area and power-consumption. Therefore, we can play many game when a multi-threshold voltage design was implemented.
Power gating/MTCMOS --> is coming soon
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I'm very sorry about my English, I will to try in my best!
Nguyen Phuc Vinh
vinh.camau@gmail.com