Low-power design lessons and reference

[roli]

Low-power design

A word to the OP, and a word to the critics (mainly user 'skygazer'):

To the OP:
It would have been nice if you would have provided references & bibliography of your nice work, especially for the sake of users who are seeking a more detailed knowledge about the subject.

To the critics:
There's no need for flaming the OP's good initiative.

Bless ALL !

 

[denmos]

Re: Low-power design

Hi all,

I'm sorry about the delay so far. I just want you to know: I am on my assignment in the US. So, I will post all my experiences about low-power design on Oct.
That will focus on how to implement the M-Vt, M-Vdd design using the EDA tools.

Have a nice day, all!

Thanks

 

[windowX]

Low-power design

good man!

 

[vlsichipdesigner]

Re: Low-power design

Dear designers,

my 2 cents in this low power discussion.

In order to reduce the power consumption, there is a requirement of an
"intelligent power management unit" I.P., which will monitor the system,

say for example:
the chip has voice and data related I.P., the Power management unit understands that the user is using only voice area of the chip and will send signal to shut down the data related portion of the logic to save power.

Another interesting stuff called as "Dynamic Voltage Frequency scaling[DVFS]" techniques!!!.

Lowering Vdd , reduces in performance, which we are not interested in.
All are greedy, rather utilize the maximum possible.
means maximum performance and minimum power consumption.
So dynamically scaling down the voltage and frequency targets in place where the performance is not a concern thereby reducing the power. As we all know reducing the voltage and frequency directly reduces the power consumption.

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
[ASIC Design School with out Fees!!!]

 

[Thinkie]

Low-power design

Frequency Throttling is another interresting technique that can be used in combination with Voltage Scaling

STA can become a nightmare when you mess around with all those parameters... but that is another story...

 

[longsun]

Re: Low-power design

Dear designers,

my 2 cents in this low power discussion.

In order to reduce the power consumption, there is a requirement of an
"intelligent power management unit" I.P., which will monitor the system,

say for example:
the chip has voice and data related I.P., the Power management unit understands that the user is using only voice area of the chip and will send signal to shut down the data related portion of the logic to save power.

Another interesting stuff called as "Dynamic Voltage Frequency scaling[DVFS]" techniques!!!.

Lowering Vdd , reduces in performance, which we are not interested in.
All are greedy, rather utilize the maximum possible.
means maximum performance and minimum power consumption.
So dynamically scaling down the voltage and frequency targets in place where the performance is not a concern thereby reducing the power. As we all know reducing the voltage and frequency directly reduces the power consumption.

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
[ASIC Design School with out Fees!!!]

Great post in low power design. "intelligent power management unit" (extendable) + DVFS

 

[crinud]

Re: Low-power design

for starting lowpower pls go through this docmunt

 

[armardu]

Low-power design

Frequency Throttling is another interresting technique that can be used in combination with Voltage Scaling

STA can become a nightmare when you mess around with all those parameters... but that is another story...

 

[shavakmm]

Re: Low-power design

Low power related articles can be found at :
https://asic-soc.blogspot.com

 

[vlsitechnology]

Low-power design

Hello Denmos could u please explain me where exactly do we use these low power techniques at wt stage.....in frontend or backend???

Reply me
Mujtaba Ahmed

 

[AdvaRes]

Re: Low-power design

Low power related articles can be found at :
https://asic-soc.blogspot.com

Thanks my colleague the link was very helpfull for me.
Also I remember that there is a forum on Low power techniques on
www.Synopsys.com

 

[rohit khandelwal]

Re: Low-power design

paper on mtcmos, one of the mostimp technique of low power vlsi