Low-power design lessons and reference

[denmos]

Hi all,
I want to show you some knowledge about low-power design in a set of lessons.
I hope it will be useful docs for your low-power knowledge. Please reply and let me know your thinking about this topic. I will post all lessons when I get your good-feedbacks.

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Lesson 1: Low-power overview:
Low power design is an increasingly common technique help reduce power dissipation in complex SOCs/ASIC. Power consumption on the chip is consumed both when the circuit is active (dynamic power) and also when it is inactive (static power).
+ Dynamic power is associated by switching of state on nets and cells. Dynamic power is absoluted by switching-frequency, load-capacitance and square of supply voltage:
P(dynamic) = a x F x C x sqr(Vdd)

+ Static power is referred to leakage power. Leakage power consumption is computed by sub-threshold leakage, gate leakage and reverse-bias junction BTBT leakage. For a particular technology process, the gate leakage and reverse-bias leakage are constant. therefore, the leakage current from Drain to Source (into a CMOS-transitor) is defined as static-power consumption:

P(static) = exp (-q x Vth / KT), Vth is threshold-voltage of gate.

So, I think we should learn how the gate delay are computed. The cell delay associated with a transistor is affected by the switching threshold voltage (Vth) and the supply voltage (Vdd):

Delay = Vdd x sqr [(Vdd - Vt), *a]

The high-speed cell delay is reference with lower threshold-voltage and higher supply-voltage. Now a day, when cmos process is scaling down to 65nm and below, the leakage consumption is 40 percent of total power-consumption.
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Sesson 2: How to reduce power consumption --> Coming soon! ....

Thanks
Nguyen Phuc Vinh
vinh.camau@gmail.com

 

[shelkerahul]

Re: Low-power design

Good work denmos,

I think we need this topic to be discussed thoroughly.
I have one doubt in this equation {P(dynamic) = a x F x C x sqr(Vdd) }. what is "a" here? and in delay calculation also.....

waiting for your Sesson-2 :wink:

 

[deh_fuhrer]

Re: Low-power design

"a" might be the switching activity..

Added after 2 minutes:

i.e, the average number of times the output goes to 0->1 and 1->0.

 

[sim_333]

Low-power design

nice equations denmos , keep sending

 

[guzhal]

Re: Low-power design

Good work Denmos,
It is easy to understand and enables the readers to read more

Continue posting all the docs reg. low power design

 

[satanix]

Re: Low-power design

Low power CMOS Digital Design,
Chandrakasan, Sheng and Broderson.

One of the classic papers in this area.
Available here:



Enjoy.

 

[denmos]

Re: Low-power design

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Sesson 2: How to reduce power consumption

Now, we continue to the next topic "how to reduce power consumption". There are a lot of techniques and different methods attack different portions of the power equation. They usually have some overhead of some sort. For your knowledge, I will point these techniques to kind of power-consumption that it saved.

Clock gating - dynamic power reducing technique

The oldest and most tried-and-true technique for reducing power is clock gating. More than 1/3 of an IC design’s dynamic power is in the chip’s clock-distribution system.

It’s a pretty simple concept: If you don’t need a clock running, shut it down. You would use the enable signal that controls the multiplexer to control the clock cell to clock the signal off. Because, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. It's free to save 20-30 percent of dynamic power consumption for sequential blocks.

Multivoltage design (M-Vdd) - dynamic-power reducing

Multivoltage design enables designers to give the critical paths and blocks in their designs access to maximum voltage for the process and specification, but the designers then reduce the voltage for less power-hungry blocks.

For example, a processor block may require a clock speed of 1.0 GHz, but a USB core may require only 30 MHz to comply with the USB protocol and thus require less voltage to run. So, if designers give the USB core only the power it needs, they can drastically reduce the overall power the design consumes.

Designers also put level-shifters between blocks that are running at different voltages and can use isolation cells to shut-down any voltage-domain is we don't need it run. Multivoltage design have many way to save your chip power consumption: multi voltage islands (w/ OR w/o shutdown mode), voltage scaling that have included voltage regulator and mode control sub-blocks into main-block.

Power-savvy memory - both dynamic and static power consumption

This is another popular technique for lowering both dynamic power and leakage is to use power-aware memories. In its simplest form, the technique involves shutting down segments of a memory array when they are not in use. Another technique in this category is body-biasing memories. In this method, designers reverse-bias a memory when it is not in use, which essentially raises the threshold voltage and in turn slows leakage.
Another technique gaining popularity is to use multimode power for memories. In this technique, designers employ memory with several power modes. Many designs employ dual-function memories so that, when the CPU accesses a memory to read or write data to run a main application, the memory receives full access to power to perform the operation. However, when the memory is not required to read or write, designers can program the memory to power down to a level at which the memory gets only enough power to retain its memory content.

Multithreshold design (M-Vth) - Static power reducing technique

About five years ago, when excessive power consumption became a problem, foundries started to offer multi-threshold voltage libraries for low-power and high-speed design. Multiple-cell libraries help designers deal with both leakage and dynamic power. A multicell library typically comprises at least two sets of identical cells that have different threshold voltages. Those with higher threshold voltage are slower but have less leakage; conversely, the cells with lower threshold voltage are faster but leak. The high-threshold-voltage cell typically has 50% less leakage than a low-threshold-voltage cell with no bad side effects, such as area gain.

To deal with leakage power using multiple types of cells, designers today employ multithreshold design. You can use high-speed cell (higher leakage) for speed-critical paths, and, use lower-speed cell for non-critical paths if you want to reduce the leakage. You also trade-off between die-area and power-consumption. Therefore, we can play many game when a multi-threshold voltage design was implemented.

Power gating/MTCMOS --> is coming soon

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I'm very sorry about my English, I will to try in my best!
Nguyen Phuc Vinh
vinh.camau@gmail.com

 

[skygazer]

Re: Low-power design

good work denmos, but all of the above looks like it has come from this page: :roll:
**broken link removed**

 

[denmos]

Re: Low-power design

Hi Skygazer and all,

Yes, it was. So I have collected them in my all convenience. I think it was easy to read and is not difficult to know, wasn't it? So, it is one of nine/ten topics about low-power design. I will re-edit some my presentations sothat we can learn how to implement low-power design.

Have a nice day! See you later!

vinh.camau@gmail.com

 

[vak]

Re: Low-power design

Hi denmos,

Great job. Thank you for sharing this information.

 

[p_shinde]

Re: Low-power design

Hi Vinh,

Good job!! waiting for ur lessons on implementation of these designs.

Thanks,
Prasad

 

[ecikin]

Low-power design

how to download these lessons?

 

[leyuanniao]

Low-power design

I just learn a low power lesson from Infineon, which use Synopsys Powercompiler tools.

 

[p_shinde]

Re: Low-power design

leyuanniao, it would be very nice if u can share something ........for all ppl over here....

 

[ece9710]

Re: Low-power design

please share your ideas about this...

Added after 3 minutes:

i am also interesting with this topic as a requirement in our design...

 

[wkong_zhu]

Low-power design

I also want to know something about clock gating.
I used to use synopsys DC to synthesis IC without power compiler.
If I use clock-gating power compiler, what should I care more about. something about timing and P&R etc.

 

[windowX]

Re: Low-power design

Hi, denmos, your presentation about how to reduce power consumption
is just the material I am looking for. Thanks very much, wish more
infomation.

 

[nbuzs]

Re: Low-power design

For low power design. the Adiabatic computing is also a very useful principle.

 

[calm]

Low-power design

low power chip testing, please!

 

[avimit]

Re: Low-power design

Hi here is my low power page:
http://www.vlsiip.com/low_power.html

Added after 6 minutes:

I also want to know something about clock gating.
I used to use synopsys DC to synthesis IC without power compiler.
If I use clock-gating power compiler, what should I care more about. something about timing and P&R etc.


Hi: You must see the timing, if it has gone worse. Also if you are using the attribute 'sync_set_reset' then you must be very careful, as some dc versions will not allow 'clock_gating' and this attribute to work in parallel.

One more thing you should look at is 'set_clock_gating_style'