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Low Dropout Regulators

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navid eidgah

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Dear Specialists,
I'm working on an LDO that has been designed in 0.18um TSMC.
I try to decrease the size of the Pass Transistor while maintaining other specs.
What are the typical sizes of these pass devices for a maximum load current of 300mA or more?
how can i check the stability and phase margin of my circuit while the LDO has just a DC input voltage?
thanks in advanc
 

hi,

I'm not sure whether you can decrease the PT size unless the previous stage supports the swing. There isn't any specific sizes for the PT, you can simulate a PMOS(alone) with the min supplly & max regualted votlage & sweep 'w', with a max allowed swing in the previous stage monitoring the current through the device. I guess this plot will fix the PT size.
 

thank you Yuvan.
would you please also describe the step by step way to see and check my circuit's frequency response in Cadence?
how can i see the poles and zeros?how can i see that my LDO is suitable for high speed conditions?
thanks again in advance
 

For such high loads it is usual to keep the transistor in the linear stage. This is because to keep the transistor in saturation at such high loads it would require really huge sizes.
Keep the gain of the Amplifier/Driver stages high so that the loop gain is high enough even with the pass transistor in linear. A high loop gain would give good regulation.

I don't know what you mean by "high speed conditions", but for good PSRR/Noise performance at high frequencies you would need a large bandwidth of the Amplifier/Driver stage.
For good load-transient performance the LDO has to charge/discharge very fast. In order to do this, you would need to place a internal decoupling capacitor which would supply the charge during the fast transients. An internal capacitor with a large enough external capacitor would be good enough for transient performance.
 

thank you a lot Nitishn5 for your complete response,
but for a transistor to offer more current, it is necessary to be operating in Saturation region,
what is the reason you said that Linear region is more preferable for higher currents?
 

You could go for a pass transistor in saturation region, but you would require huge size since W has to be big or you would need a large drop out voltage which would give poor efficiency.
If you can afford on area then you should go for a pass transistor in saturation.


That is why a transistor in linear region is preferred for high current LDOs.
 

for two transistors which are in the same situations-same size, same vth, same vg, but different vds voltages, the one which is operating is Saturation region gives more current.
isn't that true?
 
Last edited:

@navid

If you are comparing two pass transistors in an LDO, the Vds is the same since it is the Vsupply - Vregulated.
The gate voltage would be different depending on the current through the pass transistor.

If the transistor is not sized large enough, the gate voltage would be such that the pass transistor would be in linear region, else if it is large enough then it would be in saturation.

And kishore680 is right that with large transistors, when the load current is low, the transistor would be in subthreshold which is ok too.

As long as your loop gain is high enough you would have the required load/line regulation. So just keep the Amplifier/Driver stage strong.
 

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