Low Dropout Regulator Design

[piyush1991]

Hi
I have Design Op-Amp working with 1.2V Supply Voltage.
Then i have connected power transistor and feedback resistors, But as soon as i connect output of feed back resistors to the input of Op-amp all biasing voltages get changes and op amp output decreases to around 200mV and power transistors start operating in linear region and Vds=1.2mV across Power Transistor .I have used feedback resistors value around 5M-10M.
I thought it was due to loading effect So, i use voltage buffer in between Op Amp output and Power transistor input but still same thing happens
Can any one suggest me what should i do?

 

[nitishn5]

What is the ICMR or you Op-amp?
What is the Output Voltage that you are targeting?
Do the two match?

You should have designed the entire LDO together and not in parts (Error Amplifier and then Power Transistor)

 

[piyush1991]

hi
thanks nitishn5
now i have design it again all the blocks together and simulate it. It is working with DC analysis fine with no load at output with 10nF capacitor.Power transistor is operating in saturation with Vds=75mV.(it is gpdk 90 nm Technology with Cadence Virtuoso)
But as soon as i do transient analysis with connecting load resistor of 100K power transistor start working in linear region and output voltage also get change.
what steps should i follow to avoid it..?
and
how to improve current capability of LDO?
What should be the feedback resistor value rang ?

 

[nitishn5]

It seems that your power transistor is not sized properly.

Are you sure it can handle the load that you have put? Because if it is sized too small, it would require a very large Vgs to provide that current, which might put it into linear region.



An LDO is not just some Error Amplifier and some Power Transistor put together. It is a both of them in a feedback loop.
While putting together a separately designed error amplifier and a power transistor might still work, it would not be the optimum way to design the LDO.
For one thing the stability and loop gain functions would change and you have to be very lucky or very sure of your pole locations to ensure that your loop would still be stable!

 

[piyush1991]

hi
Thank you for your suggestion.
one more question is should i design LDO while load is connected or i should design with no load condition ?
if i should connect load then what should be load value ?

 

[nitishn5]

hi
Thank you for your suggestion.
one more question is should i design LDO while load is connected or i should design with no load condition ?
if i should connect load then what should be load value ?

What Load are you designing the LDO for? The LDO should be designed for the Maximum expected load.

You would also be having some transient requirements as well. The loop bandwidth must be big enough to handle the type of transients you expect.

And then would come all the other specifications like PSRR, Noise etc. (These may or may not be important depending on the application.)


The stability would have to be checked for both Full Load and No Load conditions. Depending on your frequency compensation scheme, it might affect both.