Low Dropout (LDO) Regulator Design

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This is the LDO Regulator Circuits. Please verify this and give me a idea for implementation.
 

It's the -35dB@10GHz that cracks me up. You can't get
RF switches to do that in CMOS, difficult even in an exotic
technology. And that's with a 50-ohm load. A high impedance
load on the LDO output? Forget it.

Unless you want to put a choke/cap filter downstream.
 

there is always a tradeoff between psrr and bandwidth.
so i think it would be very difficult to achieve the given specifications.
 

i think the problem needs to be dealt at system level. especially if ur expecting -40dB PSRR @ 10G.
 

hello frns...i m also locked up with the designing of ldo...i wud b hapy if anyone provides me a design n layout of ldo...
 

i am Design and implementation of various loads for on chip voltage regulator and stability analysis, provide me a schmatics diagram .
 

plz give me W/L , cap , resistor value.
 

plz tell what modification done according this fig & result.
 

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