I'm not sure what's the purpose of the code example, it's not synthesizable thus I assume it's just an exercise to be run in the simulator.
For working of the loop construct, all assignments inside the always block must be changed to blocking "=" assignments instead of non-blocking "<=". It's the suggested style for combinational always blocks and required for all variables that are re-read inside the always block.
P.S.:
Curiously I tranlated the code inside my head and was commenting it as if it was written in Verilog. As Barry told, using variables for all data that are re-read inside the process solves the problem.