Looping with variable parameter not working

[nageshnaik]

i want to make a loop that repeats itself a variable number of times according to the input. i have worked out a code for it. This code compiles well but a output i get zero as answer. Can anyone help me rectify this issue.

i am giving both the uut and tb. Please help me rectify the issue.

UUT:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity loopagain is
 Port (    a : in  STD_LOGIC_VECTOR (15 downto 0);
           b : in  STD_LOGIC_VECTOR (15 downto 0);
           y : out  STD_LOGIC_VECTOR (15 downto 0));
end loopagain;
 
architecture Behavioral of loopagain is
 
signal sh1 :std_logic_vector(15 downto 0) := (others => '0');
signal s1 : bit_vector(15 downto 0);
signal k : bit_vector(15 downto 0);
signal lp : std_logic_vector(15 downto 0) := (others => '0');
 
begin
 
process (a,b)
begin
lp <= b;
s1 <= TO_BITVECTOR(a);
while (lp > 0) loop
    k <= s1 sll 1;
    s1 <= k;
    lp <= lp - "0000000000000001";
end loop;   
    
sh1 <= to_stdlogicvector(k) ;
y <= sh1;
 
end process;
 
 
end Behavioral;

---

Testbench:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY loopagaintb IS
END loopagaintb;
 
ARCHITECTURE behavior OF loopagaintb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT loopagain
    PORT(
         a : IN  std_logic_vector(15 downto 0);
         b : IN  std_logic_vector(15 downto 0);
         y : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal a : std_logic_vector(15 downto 0) := (others => '0');
   signal b : std_logic_vector(15 downto 0) := (others => '0');
 
    --Outputs
   signal y : std_logic_vector(15 downto 0);
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: loopagain PORT MAP (
          a => a,
          b => b,
          y => y
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
  
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100ms.
      wait for 100ns;   
 
     a <= "0000000000000011";
      b <= "0000000000000001";
 
      -- insert stimulus here 
 
      wait;
   end process;
 
END;

---

Thank you in advance.

 

[FvM]

I'm not sure what's the purpose of the code example, it's not synthesizable thus I assume it's just an exercise to be run in the simulator.

For working of the loop construct, all assignments inside the always block must be changed to blocking "=" assignments instead of non-blocking "<=". It's the suggested style for combinational always blocks and required for all variables that are re-read inside the always block.

P.S.:
Curiously I tranlated the code inside my head and was commenting it as if it was written in Verilog. As Barry told, using variables for all data that are re-read inside the process solves the problem.

 

[barry]

I don't really know what you are trying to do here, but the problem is most likely due to the fact that you are using a signal rather than a variable for lp. Basically, signals only change value at the end of a process; variables change immediately.

 

[nageshnaik]

I'm not sure what's the purpose of the code example, it's not synthesizable thus I assume it's just an exercise to be run in the simulator.

For working of the loop construct, all assignments inside the always block must be changed to blocking "=" assignments instead of non-blocking "<=". It's the suggested style for combinational always blocks and required for all variables that are re-read inside the always block.

P.S.:
Curiously I tranlated the code inside my head and was commenting it as if it was written in Verilog. As Barry told, using variables for all data that are re-read inside the process solves the problem.

actually i am trying to work on floating point operation wherein i have to adjust the mantissa according to exponent difference. so i was trying to workout some loops that repeat themselves on the value they receive and not on a preassigned value, something like a variable loop

- - - Updated - - -

I don't really know what you are trying to do here, but the problem is most likely due to the fact that you are using a signal rather than a variable for lp. Basically, signals only change value at the end of a process; variables change immediately.

actually i am trying to work on floating point operation wherein i have to adjust the mantissa according to exponent difference. so i was trying to workout some loops that repeat themselves on the value they receive and not on a preassigned value, something like a variable loop

 

[TrickyDicky]

but what is the end goal? as FvM Already said, this code cannot be synthesised for an FPGA, or into any hardware.

 

[FvM]

A shift_left() function can be used with variable shift count and is synthesizable. It can be implemented as a multiplexer tree for each bit and should be sufficiently fast for reasonable bit widths. Alternatively the shift operation can be performed sequentially in a shift register, needing N clock cycles.