can anyone provide me synthesizable vhdl /verilog code for a simple adpll.
adpll comprises of pfd,
up/down counter loop filter and
divide by n dco.
if u have any other architecture its fine,
please help me its urgent
Hi, do you still have a copy of the verilog code from the website "http://www-unix.ecs.umass.edu"? or do you have a working verilog code for adpll? i am having troubles with mine. :/