Looking for synthesizable VHDL /Verilog code for a simple adpll

[janarthanan]

can anyone provide me synthesizable vhdl /verilog code for a simple adpll.
adpll comprises of pfd,
up/down counter loop filter and
divide by n dco.
if u have any other architecture its fine,
please help me its urgent

 

[mm6349]

Re: code for adpll

you may take a look on this website ..

**broken link removed**

I didn't test the code whether it is usable or not.. you can try and share your experience..

mm//

 

[janarthanan]

Re: code for adpll

i tried it. but i dont know whether it is working or not.
the output is not seems to be working becoz there is no indication of output being locked

 

[Iouri]

code for adpll

not sure why do you need it for???

 

[janarthanan]

Re: code for adpll

actually its my final year project.
my project title is adpll design and jitter analysis.

for jittter measurement and jitter reduction, i need a synthesizable adpll code.

adpll is to be used for clock generation and clock multiplication.

 

[ajhunt18]

Re: code for adpll

i tried it. but i dont know whether it is working or not.
the output is not seems to be working becoz there is no indication of output being locked

Hi, do you still have a copy of the verilog code from the website "http://www-unix.ecs.umass.edu"? or do you have a working verilog code for adpll? i am having troubles with mine. :/