shitansh
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Hi,
can any one provide some material or docs related to low power ASIC RTL design.
In my need, i need to work on the low power RTL design where, I need to instantiate some power domain crossing cells in the existing RTL and have to write a constrain file for VCS (synopsis simulation tool) for doing the proper verification of these cells.
Waiting for your reply,
Thanks,
Shitansh Vaghela
can any one provide some material or docs related to low power ASIC RTL design.
In my need, i need to work on the low power RTL design where, I need to instantiate some power domain crossing cells in the existing RTL and have to write a constrain file for VCS (synopsis simulation tool) for doing the proper verification of these cells.
Waiting for your reply,
Thanks,
Shitansh Vaghela